Re: [PATCH net-next v4 1/8] dt-bindings: net: add Xilinx TSN Endpoint Ethernet MAC

[Andrew Lunn <andrew@lunn.ch>]

> +      xlnx,max-learning-entries:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 256
> +        maximum: 1920
> +        default: 1920
> +        description:
> +          Maximum number of addresses the hardware address learning engine
> +          can learn on each network port (MAC1 and MAC2). This is the
> +          MAX_LEARNING_ENTRIES IP configuration parameter, and no register
> +          reports it. The endpoint port does not take part in hardware
> +          address learning.

Is this a synthesis parameter? No other switch that i know of has it
in DT. The driver hard codes the value based on the compatible. Why
does that not work for you?

> +      mdio-1:
> +        $ref: /schemas/net/mdio.yaml#
> +        description:
> +          MDIO bus controller for MAC1. Registers reside inside the mac1
> +          reg-names window.
> +        unevaluatedProperties: false
> +
> +      mdio-2:
> +        $ref: /schemas/net/mdio.yaml#
> +        description:
> +          MDIO bus controller for MAC2. Registers reside inside the mac2
> +          reg-names window.
> +        unevaluatedProperties: false

How hard coded into the design is the number of ports? The way the DT
is structured, it does not seem easy to add another port. It is more
normal to put all port properties within one node, so you just need to
cookie cutter that node, not add new nodes all other the place.

> +        switch@38000 {
> +            compatible = "xlnx,tsn-switch";
> +            reg = <0x38000 0x8000>,
> +                  <0x00000 0x14000>,
> +                  <0x20000 0x14000>;
> +            reg-names = "switch", "mac1", "mac2";

> +            mdio-1 {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +                phy0: ethernet-phy@0 {
> +                    reg = <0>;
> +                };
> +            };
> +
> +            mdio-2 {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +                phy1: ethernet-phy@1 {
> +                    reg = <1>;
> +                };
> +            };

Interesting that this is address 1, where as the other is address 0.
Just to be sure, there are two fully independent MDIO bus masters?

This 


> +
> +            ethernet-ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                ethernet-port@0 {
> +                    reg = <0>;
> +                    ethernet = <&ep_mac>;
> +                    phy-mode = "internal";
> +
> +                    fixed-link {
> +                        speed = <1000>;
> +                        full-duplex;
> +                    };
> +                };
> +
> +                ethernet-port@1 {
> +                    reg = <1>;
> +                    phy-handle = <&phy0>;
> +                    phy-mode = "rgmii-id";
> +                };
> +
> +                ethernet-port@2 {
> +                    reg = <2>;
> +                    phy-handle = <&phy1>;
> +                    phy-mode = "rgmii-id";

Are these two PHY internal or external? Using rgmii internally is O.K,
but odd. Normally 'GMII' or 'internal' would be used.

    Andrew