[PATCH] x86, quirks: Add workaround for AMD F16h Erratum792

[Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>]

The workaround for this Erratum is included in AGESA. But BIOSes spun
only after Jan2014 will have the fix (atleast server versions of the
chip). The erratum affects both client and server platforms and since
we cannot say with certainity that ALL BIOSes on systems out in the
field will have the fix, we should probably insulate ourselves in case
BIOS does not do the right thing or someone is using old BIOSes.

Refer Revision Guide for AMD F16h models 00h-0fh, document 51810
Rev. 3.04, November2013 for details on the Erratum.

Tested the patch on Fam16h server platform and works fine.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/kernel/quirks.c |   31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 04ee1e2..e55ae02 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -571,3 +571,34 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
 			quirk_amd_nb_node);
 
 #endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Apply AMD Fam16h Erratum792
+ * see Revision Guide for AMD F16h models 00h-0fh,
+ * document 51810 rev. 3.04, Nov 2013
+ */
+static void quirk_amd_dram_scrub(struct pci_dev *dev)
+{
+	u32 val;
+
+	/* Suggested workaround:
+	 * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
+	 */
+	pci_read_config_dword(dev, 0x58, &val);
+	if (val & 0x1F) {
+		val &= ~(0x1F);
+		pci_write_config_dword(dev, 0x58, val);
+	}
+
+	pci_read_config_dword(dev, 0x5C, &val);
+	if (val & BIT(0)) {
+		val &= ~BIT(0);
+		pci_write_config_dword(dev, 0x5c, val);
+	}
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
+			quirk_amd_dram_scrub);
+
+#endif
-- 
1.7.9.5