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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a497f2073bsm4511679a91.8.2026.09.29.02.26.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Sep 2026 02:26:48 -0700 (PDT) Message-ID: <138bbe2f-2871-4541-80c9-c7867e1b1481@oss.qualcomm.com> Date: Tue, 29 Sep 2026 14:55:17 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] mailbox: qcom-cpucp: read mbox hardware register using readq() To: Sivansh Gupta Cc: Jassi Brar , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260928052940.688105-1-sivansh.gupta@oss.qualcomm.com> Content-Language: en-US From: Sibi Sankar In-Reply-To: <20260928052940.688105-1-sivansh.gupta@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI5MDAzNyBTYWx0ZWRfX1aHc+748RvqL V8GnS9yfcFY+Ry+Biz/tsA4+2oJxTCY19nwqbeV1Bf+dhDyxnZQZALwhkJSJkQUBebA1Hdz7vDU LuER5YCXThdw8s1+AgGKh8nlQAgE32M= X-Authority-Analysis: v=2.4 cv=SIbXx+vH c=1 sm=1 tr=0 ts=6abb845a cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=dvwXRZ08jinNhRNPmSsA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI5MDAzNyBTYWx0ZWRfX5sur6/vWt8mX gCjThq7YnIXktAmRFxY//I69zOdTchfBP/gGt4hUoccTKHFi71mt5OZPTUw99CXYDgd0oxqZFru ejkZEh+tQDj97Jbg3ScMoDb2BcUX6Q7o08l46TWIE6N+sT8P4OS7+fz5k5L7q35YwogZSDIOSPy CiD+AiJZAWEHc7z9M28AFI76MwbyoXbYJpQKdWNEC9TOI6rsfaK8kJpVMMer5r7VwA6caFUvwt6 9lP+aU5NGMR16Z6nUvyWhmvQtUcvNHZMwvq8L/uEACnfKXzKzRePxqVXVLXJ00CvxXz0yyP2Ukc QDhnFrPPHGqI5eJnz/EEV2/EVlUK5O7O4EW4sEksjGNn4BE4JZDqh5h7GnROyS7lu/7ahbMqNkT hLooGy5HbX/50131J+nBo+Mf3ZCwFQb/ZjP/CiQ8RVnlbAibx6vXJPCX4mIo29v5LBLtHt7wigI Ab46l8fve1IM2ruKLZQ== X-Proofpoint-GUID: jLceyAKDJw7AUxlDEuPrCcifkkcWoEPD X-Proofpoint-ORIG-GUID: jLceyAKDJw7AUxlDEuPrCcifkkcWoEPD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609290037 On 9/28/26 10:59, Sivansh Gupta wrote: > Mailbox hardware registers are 64 bit wide, but the interrupt handler > currently reads only 32 bits with readl() at offset 0x4 (upper 32 > bits). This returns an incorrect value, while reading using readq() > returns the expected value. > > Use readq() to access the 64 bit register and pass the expected value > to the mailbox client. Mailbox hardware registers are 64 bit wide, but the interrupt handler currently reads only 32 bits with readl() at offset 0x4 (upper 32 bits). This results in a masked out value being passed on to the mailbox clients. Fix this by using readq instead and pass on the correct value to the mailbox clients. ^^ seems more appropriate with these minor nits fixed. Reviewed-by: Sibi Sankar > > Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller") > Signed-off-by: Sivansh Gupta > --- > v3: > - Removed references to an out of tree driver to focus on the incorrect > value returned by readl() > https://lore.kernel.org/all/93ce8588-7500-45da-9b9a-424c202590cf@oss.qualcomm.com/#t > > v2: > - Expanded the commit message to explain why this change is required. > > drivers/mailbox/qcom-cpucp-mbox.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c > index 862e45e8fbd5..0b584d9aad6c 100644 > --- a/drivers/mailbox/qcom-cpucp-mbox.c > +++ b/drivers/mailbox/qcom-cpucp-mbox.c > @@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) > status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); > > for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { > - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); > + u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i)); > struct mbox_chan *chan = &cpucp->chans[i]; > unsigned long flags; >