From: Stephane Eranian <eranian@google.com>
To: linux-kernel@vger.kernel.org
Cc: peterz@infradead.org, mingo@elte.hu, acme@redhat.com,
ak@linux.intel.com, zheng.z.yan@intel.com
Subject: [PATCH v1 07/10] perf/x86/uncore: allow more than one fixed counter per box
Date: Mon, 3 Feb 2014 13:55:39 +0100 [thread overview]
Message-ID: <1391432142-18723-8-git-send-email-eranian@google.com> (raw)
In-Reply-To: <1391432142-18723-1-git-send-email-eranian@google.com>
This patch modifies some of the helper functions to support
more than one fixed counter per uncore PCI PMU box.
Signed-off-by: Stephane Eranian <eranian@google.com>
---
arch/x86/kernel/cpu/perf_event_intel_uncore.c | 4 ++--
arch/x86/kernel/cpu/perf_event_intel_uncore.h | 22 +++++++++++++---------
2 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 2980994c..69a4ad0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -2777,8 +2777,8 @@ static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_eve
hwc->idx = idx;
hwc->last_tag = ++box->tags[idx];
- if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
- hwc->event_base = uncore_fixed_ctr(box);
+ if (hwc->idx >= UNCORE_PMC_IDX_FIXED) {
+ hwc->event_base = uncore_fixed_ctr(box, idx);
hwc->config_base = uncore_fixed_ctl(box);
return;
}
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index 433c180..c63a3ff 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -538,9 +538,18 @@ static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
return box->pmu->type->fixed_ctl;
}
-static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
+static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
+{
+ return box->pmu->type->fixed_ctr_bits;
+}
+
+static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box,
+ int idx)
{
- return box->pmu->type->fixed_ctr;
+ int bits = uncore_fixed_ctr_bits(box);
+ int bytes = round_up(bits, 8);
+
+ return idx * bytes + box->pmu->type->fixed_ctr;
}
static inline
@@ -554,11 +563,6 @@ static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
return box->pmu->type->perf_ctr_bits;
}
-static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
-{
- return box->pmu->type->fixed_ctr_bits;
-}
-
static inline
unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
{
@@ -627,10 +631,10 @@ unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
}
static inline
-unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
+unsigned uncore_fixed_ctr(struct intel_uncore_box *box, int idx)
{
if (box->pci_dev)
- return uncore_pci_fixed_ctr(box);
+ return uncore_pci_fixed_ctr(box, idx);
else
return uncore_msr_fixed_ctr(box);
}
--
1.7.9.5
next prev parent reply other threads:[~2014-02-03 12:56 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-03 12:55 [PATCH v1 00/10] perf/x86/uncore: add support for SNB/IVB/HSW integrated memory controller PMU Stephane Eranian
2014-02-03 12:55 ` [PATCH v1 01/10] perf/x86/uncore: fix initialization of cpumask Stephane Eranian
2014-02-10 2:49 ` Yan, Zheng
2014-02-11 11:12 ` Stephane Eranian
2014-02-03 12:55 ` [PATCH v1 02/10] perf/x86/uncore: add ability to customize pmu callbacks Stephane Eranian
2014-02-03 12:55 ` [PATCH v1 03/10] perf/x86/uncore: do not assume PCI fixed ctrs have more than 32 bits Stephane Eranian
2014-02-10 3:11 ` Yan, Zheng
2014-02-11 13:54 ` Stephane Eranian
2014-02-03 12:55 ` [PATCH v1 04/10] perf/x86/uncore: add PCI ids for SNB/IVB/HSW IMC Stephane Eranian
2014-02-03 12:55 ` [PATCH v1 05/10] perf/x86/uncore: make hrtimer timeout configurable per box Stephane Eranian
2014-02-03 12:55 ` [PATCH v1 06/10] perf/x86/uncore: move uncore_event_to_box() and uncore_pmu_to_box() Stephane Eranian
2014-02-03 12:55 ` Stephane Eranian [this message]
2014-02-10 3:17 ` [PATCH v1 07/10] perf/x86/uncore: allow more than one fixed counter per box Yan, Zheng
2014-02-03 12:55 ` [PATCH v1 08/10] perf/x86/uncore: add SNB/IVB/HSW client uncore memory controller support Stephane Eranian
2014-02-10 6:27 ` Yan, Zheng
2014-02-03 12:55 ` [PATCH v1 09/10] perf/x86/uncore: add hrtimer to SNB uncore IMC PMU Stephane Eranian
2014-02-10 6:04 ` Yan, Zheng
2014-02-03 12:55 ` [PATCH v1 10/10] perf/x86/uncore: use MiB unit for events for SNB/IVB/HSW IMC Stephane Eranian
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1391432142-18723-8-git-send-email-eranian@google.com \
--to=eranian@google.com \
--cc=acme@redhat.com \
--cc=ak@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@elte.hu \
--cc=peterz@infradead.org \
--cc=zheng.z.yan@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome