From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753653AbaBJRdU (ORCPT ); Mon, 10 Feb 2014 12:33:20 -0500 Received: from top.free-electrons.com ([176.31.233.9]:59742 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753596AbaBJRdK (ORCPT ); Mon, 10 Feb 2014 12:33:10 -0500 From: Gregory CLEMENT To: Mike Turquette Cc: Thomas Petazzoni , Ezequiel Garcia , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org, Lior Amsalem , Tawfik Bayouk , Nadav Haklai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory CLEMENT Subject: [PATCH 5/6] dt: Update binding information for mvebu core clocks with Armada 380/385 Date: Mon, 10 Feb 2014 18:32:48 +0100 Message-Id: <1392053569-28037-6-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1392053569-28037-1-git-send-email-gregory.clement@free-electrons.com> References: <1392053569-28037-1-git-send-email-gregory.clement@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thomas Petazzoni Add the binding information for the core clocks of the Armada 380 and Armada 385 SoCs Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/clock/mvebu-core-clock.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt index 62fc34a1506d..307a503c5db8 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt @@ -17,6 +17,12 @@ The following is a list of provided IDs and clock names on Armada 375: 2 = l2clk (L2 Cache clock) 3 = ddrclk (DDR clock) +The following is a list of provided IDs and clock names on Armada 380/385: + 0 = tclk (Internal Bus clock) + 1 = cpuclk (CPU clock) + 2 = l2clk (L2 Cache clock) + 3 = ddrclk (DDR clock) + The following is a list of provided IDs and clock names on Kirkwood and Dove: 0 = tclk (Internal Bus clock) 1 = cpuclk (CPU0 clock) @@ -27,6 +33,7 @@ Required properties: - compatible : shall be one of the following: "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks + "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks "marvell,dove-core-clock" - for Dove SoC core clocks "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) -- 1.8.1.2