From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755300AbaCDRR5 (ORCPT ); Tue, 4 Mar 2014 12:17:57 -0500 Received: from mail-ie0-f175.google.com ([209.85.223.175]:52388 "EHLO mail-ie0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755180AbaCDRRy (ORCPT ); Tue, 4 Mar 2014 12:17:54 -0500 From: Soren Brinkmann To: Russell King , Greg Kroah-Hartman , Jiri Slaby Cc: Michal Simek , Peter Crosthwaite , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, Olof Johansson , Arnd Bergmann , Kevin Hilman , Soren Brinkmann Subject: [PATCH RFC 5/6] ARM: zynq: DT: Migrate UART to Cadence binding Date: Tue, 4 Mar 2014 09:17:28 -0800 Message-Id: <1393953449-28551-6-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 1.9.0.1.g4196000 In-Reply-To: <1393953449-28551-1-git-send-email-soren.brinkmann@xilinx.com> References: <1393953449-28551-1-git-send-email-soren.brinkmann@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Zynq UART is Cadence IP and the driver has been renamed accordingly. Migrate the DT to use the new binding for the UART driver. Signed-off-by: Soren Brinkmann Acked-by: Peter Crosthwaite --- arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 8b67b19392ec..a229a14834ce 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -67,19 +67,19 @@ }; uart0: uart@e0000000 { - compatible = "xlnx,xuartps"; + compatible = "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: uart@e0001000 { - compatible = "xlnx,xuartps"; + compatible = "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; -- 1.9.0.1.g4196000