From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752028AbbJEDID (ORCPT ); Sun, 4 Oct 2015 23:08:03 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:33578 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751495AbbJEDIB (ORCPT ); Sun, 4 Oct 2015 23:08:01 -0400 X-AuditID: cbfee68f-f796f6d0000014a4-e8-5611e98eda89 Date: Mon, 05 Oct 2015 03:07:58 +0000 (GMT) From: Sarbojit Ganguly Subject: [PATCH v2] arm: Adding support for atomic half word exchange To: linux@arm.linux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com Cc: CatalinMarinas@samsung.com (Catalin.Marinas@arm.com), linux-arm-kernel@lists.infradead.org, peterz@infradead.org, Waiman.Long@hp.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, suneel@samsung.com, SHARAN ALLUR , VIKRAM MUPPARTHI Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20151005030455699@ganguly.s Msgkey: 20151005030455699@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20151005030455699@ganguly.s X-ParentMTR: X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <1394429506.566981444014475210.JavaMail.weblogic@epmlwas08c> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGIsWRmVeSWpSXmKPExsWyRsSkVrfvpWCYwYNHlhaXd81hc2D0+LxJ LoAxissmJTUnsyy1SN8ugStjxsprrAX7hCouTm1gaWD8I9jFyMEhJKAi0TcpoouRk0NCwETi 9NILbBC2mMSFe+uBbC6gkqWMEt8bdrDBFF3ua2KESMxhlNizaDVYggVo0NlFL5lAbDYBfYnT +yFsYQFXicY/i1lBbBGBaImWb9/YQZqZBa4ySUw9/oEFJCEkIC/R/mI7WAOvgKDEyZlPWCC2 KUnMOjiRFSKuLPFm/jdWiLicxJKpl5kgbF6JGe1PWWDi076uYYawpSXOz9rACPPO4u+PoeL8 Esdu74DqFZCYeuYgVI26xOOOPewQNp/EmoVvWWDqd51azgyzq2Hjb6gaCYmtLU/A7mEWUJSY 0v2QHcI2kDiyaA4rul94BTwkZkybywzyvITARA6J702TmCYwKs1CUjcLyaxZSGYhq1nAyLKK UTS1ILmgOCm9yFivODG3uDQvXS85P3cTIzA5nP73rH8H490D1ocYBTgYlXh4JZIEw4RYE8uK K3MPMZoCI2ois5Rocj4wBeWVxBsamxlZmJqYGhuZW5opifMulPoZLCSQnliSmp2aWpBaFF9U mpNafIiRiYNTqoFxtXq6AsP1BZP2zVnhqu6rYC0bzRYVrvOAqeiqRsPOB0drRHjWz2K6fOFN +oWbnQVu71wSEufcfflEVe9i25eNMw7JmlZkuO5UPtVum3/32I8DMfZXmM/pvk238DnyKMzz c8Btn9poBsd9IY9FRCqPOH0zE/WrbfyduHyFoKTTrWmpPIYtj/YpsRRnJBpqMRcVJwIAIE9A LQkDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOKsWRmVeSWpSXmKPExsVy+t/tft2+l4JhBj8uG1lc3jWHzYHR4/Mm uQDGqDSbjNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCh SgpliTmlQKGAxOJiJX07m6L80pJUhYz84hJbpWhDcyM9IwM9UyM9Q9NYK0MDAyNToJqEtIwZ K6+xFuwTqrg4tYGlgfGPYBcjB4eQgIpE36SILkZODgkBE4nLfU2MELaYxIV769m6GLmASuYw SuxZtJoNJMECVH920UsmEJtNQF/i9H4IW1jAVaLxz2JWEFtEIFqi5ds3dpBmZoGrTBJTj39g AUkICchLtL/YDtbAKyAocXLmExaIbUoSsw5OZIWIK0u8mf+NFSIuJ7Fk6mUmCJtXYkb7UxaY +LSva5ghbGmJ87M2wF29+PtjqDi/xLHbO6B6BSSmnjkIVaMu8bhjDzuEzSexZuFbFpj6XaeW M8Psatj4G6pGQmJryxOwe5gFFCWmdD9kh7ANJI4smsOK7hdeAQ+JGdPmMk9glJ2FJDULSfss JO3IahYwsqxiFE0tSC4oTkqvMNIrTswtLs1L10vOz93ECE5EzxbtYPx33voQowAHoxIPr0SS YJgQa2JZcWXuIUYJDmYlEV7VF0Ah3pTEyqrUovz4otKc1OJDjKbAaJvILCWanA9Mknkl8YbG JuamxqYWBobm5mZK4rw39jKECQmkJ5akZqemFqQWwfQxcXBKNTAeOSvw8NGZF5N2vU2567lc q/R3uPkGv2Af8/mbxD1zJXMS/jXppz+qXLu2nHfr+WUeadrTa+QV65Zvvbt/sflVDo/YL8XH 661UH523teHOCukQ5Xg7aavRPfcynpAJzxYanl0vdX/vln+melf1Dk9z3L4xfueXnw4c60uu /PontrHQ1EdPJj5eiaU4I9FQi7moOBEAPA8k21oDAAA= DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t95388eb004787 Hello Will, This is my second version of the patch which covers the byte exclusive case as pointed out by you. Please share your opinion on this. v1-->v2 : Extended the guard code to cover the byte exchange case as well following opinion of Will Deacon. Checkpatch has been run and issues were taken care of. Since support for half-word atomic exchange was not there and Qspinlock on ARM requires it, modified __xchg() to add support for that as well. ARMv6 and lower does not support ldrex{b,h} so, added a guard code to prevent build breaks. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 916a274..a53cbeb 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size switch (size) { #if __LINUX_ARM_ARCH__ >= 6 +#if !defined(CONFIG_CPU_V6) case 1: asm volatile("@ __xchg1\n" "1: ldrexb %0, [%3]\n" @@ -49,6 +50,22 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; + + /* + * Half-word atomic exchange, required + * for Qspinlock support on ARM. + */ + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" -- {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I