From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751990AbaEBJeD (ORCPT ); Fri, 2 May 2014 05:34:03 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4234 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751015AbaEBJd4 (ORCPT ); Fri, 2 May 2014 05:33:56 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 02 May 2014 02:24:18 -0700 From: Alexandre Courbot To: Ben Skeggs CC: Thierry Reding , , , , , , Alexandre Courbot Subject: [PATCH v4 7/9] drm/nouveau/graph: pad firmware code at load time Date: Fri, 2 May 2014 18:32:40 +0900 Message-ID: <1399023162-13159-8-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1399023162-13159-1-git-send-email-acourbot@nvidia.com> References: <1399023162-13159-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Pad the microcode to a multiple of 0x40 words, otherwise firmware will fail to run from non-prepadded firmware files. Signed-off-by: Alexandre Courbot Reviewed-by: Thierry Reding --- drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index 83dca0700ae5..bf7bdb1f291e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -894,6 +894,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, nv_wr32(priv, fuc_base + 0x0188, i >> 6); nv_wr32(priv, fuc_base + 0x0184, code->data[i]); } + + /* code must be padded to 0x40 words */ + for (; i & 0x3f; i++) + nv_wr32(priv, fuc_base + 0x0184, 0); } static void -- 1.9.2