From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757730AbaEFN6z (ORCPT ); Tue, 6 May 2014 09:58:55 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:60305 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757692AbaEFN6w (ORCPT ); Tue, 6 May 2014 09:58:52 -0400 From: Sricharan R To: , , , , , , , , , , , , , , , , , CC: Sricharan R Subject: [PATCH V5 3/3] arm: dts: dra7: Add routable-irqs property for gic node Date: Tue, 6 May 2014 19:26:19 +0530 Message-ID: <1399384579-25620-4-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399384579-25620-1-git-send-email-r.sricharan@ti.com> References: <1399384579-25620-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Signed-off-by: Sricharan R Signed-off-by: Nishanth Menon --- [V5] Rebased and corrected routable irqs from 160 to 192 arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 52e4bd0..cec826f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -72,6 +72,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <192>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5