From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758194AbaELXbb (ORCPT ); Mon, 12 May 2014 19:31:31 -0400 Received: from mail-by2lp0235.outbound.protection.outlook.com ([207.46.163.235]:35924 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752696AbaELXb1 (ORCPT ); Mon, 12 May 2014 19:31:27 -0400 From: To: , , , , , , , , , , CC: , , , , , , Subject: [PATCHv4 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC Date: Mon, 12 May 2014 18:36:56 -0500 Message-ID: <1399937817-2202-3-git-send-email-tthayer@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399937817-2202-1-git-send-email-tthayer@altera.com> References: <1399937817-2202-1-git-send-email-tthayer@altera.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.232;CTRY:US;IPV:NLI;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019001)(6009001)(199002)(189002)(79102001)(77156001)(86362001)(50466002)(93916002)(47776003)(20776003)(81342001)(77982001)(36756003)(33646001)(87286001)(6806004)(44976005)(81542001)(83322001)(575784001)(80022001)(19580405001)(97736001)(87936001)(16796002)(31966008)(74502001)(74662001)(48376002)(92726001)(92566001)(86152002)(2201001)(50986999)(76176999)(4396001)(50226001)(62966002)(85852003)(19580395003)(99396002)(102836001)(89996001)(84676001)(46102001)(42186004)(2009001)(83072002)(76482001)(88136002)(921003)(1121002)(83996005)(2101003);DIR:OUT;SFP:1102;SCL:1;SRVR:BL2FFO11HUB033;H:SJ-ITEXEDGE02.altera.priv.altera.com;FPR:;MLV:sfv;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Forefront-PRVS: 0209425D0A Authentication-Results: spf=softfail (sender IP is 66.35.236.232) smtp.mailfrom=tthayer@altera.com; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thor Thayer Addition of the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. v2: Changes to SoC EDAC source code. v3: Fix typo in device tree documentation. v4: No changes - bump version for consistency. Signed-off-by: Thor Thayer --- .../bindings/arm/altera/socfpga-sdram-edac.txt | 12 ++++++++++++ arch/arm/boot/dts/socfpga.dtsi | 5 +++++ 2 files changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt new file mode 100644 index 0000000..431e98b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt @@ -0,0 +1,12 @@ +Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] + +Required properties: +- compatible : should contain "altr,sdram-edac"; +- interrupts : Should contain the SDRAM ECC IRQ in the + appropriate format for the IRQ controller. + +Example: + sdramedac@0 { + compatible = "altr,sdram-edac"; + interrupts = <0 39 4>; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 6ce912e..a0ea69b 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -681,6 +681,11 @@ reg = <0xffc25000 0x1000>; }; + sdramedac@0 { + compatible = "altr,sdram-edac"; + interrupts = <0 39 4>; + }; + rstmgr@ffd05000 { compatible = "altr,rst-mgr"; reg = <0xffd05000 0x1000>; -- 1.7.9.5