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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b353f86f974sm554921166b.40.2025.09.27.05.25.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 27 Sep 2025 05:25:10 -0700 (PDT) Message-ID: <13eeb653-390e-4f71-aa6c-d048bbf988ab@oss.qualcomm.com> Date: Sat, 27 Sep 2025 14:25:09 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] arm64: dts: qcom: glymur: Describe display related nodes To: Dmitry Baryshkov , Abel Vesa Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pankaj Patil , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-dts-qcom-glymur-crd-add-edp-v1-0-20233de3c1e2@linaro.org> <20250925-dts-qcom-glymur-crd-add-edp-v1-1-20233de3c1e2@linaro.org> <43jgqfcw2nnasdnskfdri5swddr6kunvvp6oxzqibnlvyc4jd2@4y6x7fy5shq2> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAyOSBTYWx0ZWRfXzK4I+e8o+yBh 2ddHXxdlMvgaKWUPd/GcmO0xLU97bck1Mz9GuhKm+kTVSADofnfQpRcav4zqIB5iIJzJO6CoGdR Edncm4jm4IY1/30oxmqapQF1T/5flplucac2ofggU/qJMQEPy/UY2LZQ2Yu9JAyAcqAPzDeTUbw 0bLeUuY8Ac3rc8IRMC/JcXt/SqAF7wn0PAXfk+WY0t2x6Gp4F7pz2oUnXGK0J/CkBwXcsEYQPps lAjo1rlSs3/X4oP4oBpcCwno1qmAl4Bk53QUqxBSuWNA0DAxMbWJzs9/uQZKF2rACQiRC9ShLZt 0IO1ekbGis9X1Kbw7NHQkC5NMmGh76RWk8J/O90LCtOpjAQ1TDLsbUgYXqPvHJsp8DafvYs5UhM GQBqryZRdfJEEdfGZaaepJnDEDcFUA== X-Proofpoint-GUID: J6Lcj2cMODjYU6Rk8k0X3gApoOrwPk1B X-Authority-Analysis: v=2.4 cv=OMkqHCaB c=1 sm=1 tr=0 ts=68d7d7a9 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=KKAkSRfTAAAA:8 a=DRieHXADPiE3VOnx0JMA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: J6Lcj2cMODjYU6Rk8k0X3gApoOrwPk1B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-27_03,2025-09-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270029 On 9/27/25 12:33 AM, Dmitry Baryshkov wrote: > On Fri, Sep 26, 2025 at 09:50:22AM +0300, Abel Vesa wrote: >> On 25-09-25 20:11:11, Dmitry Baryshkov wrote: >>> On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote: >>>> The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort >>>> controllers. Describe them along with display controller and the eDP >>>> PHY. Then, attach the combo PHYs link and vco_div clocks to the Display >>>> clock controller and link up the PHYs and DP endpoints in the graph. >>>> >>>> Signed-off-by: Abel Vesa >>>> --- >>>> arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++- >>>> 1 file changed, 484 insertions(+), 8 deletions(-) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >>>> index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644 >>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >> >> [...] >> >>>> + mdss_dp0: displayport-controller@af54000 { >>>> + compatible = "qcom,glymur-dp"; >>>> + reg = <0x0 0xaf54000 0x0 0x104>, >>>> + <0x0 0xaf54200 0x0 0xc0>, >>>> + <0x0 0xaf55000 0x0 0x770>, >>>> + <0x0 0xaf56000 0x0 0x9c>, >>>> + <0x0 0xaf57000 0x0 0x9c>; >>>> + >>>> + interrupts-extended = <&mdss 12>; >>>> + >>>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, >>>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; >>> >>> No pixel1 clock? >> >> Will add it in next version. Everywhere. > > Except DP3, if I'm not mistaken. $ rg PIXEL1 drivers/clk/qcom/dispcc-glymur.c 1841: [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1842: [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1855: [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1856: [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1869: [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1870: [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, looks like it Konrad