From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
To: <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pm@vger.kernel.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
<devicetree@vger.kernel.org>,
Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Subject: [PATCH 10/13] ARM: tegra: Enable the DFLL on the Jetson TK1
Date: Fri, 11 Jul 2014 00:42:46 +0300 [thread overview]
Message-ID: <1405028569-14253-11-git-send-email-ttynkkynen@nvidia.com> (raw)
In-Reply-To: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com>
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 83 ++++++++++++++++++++++++++++++-
1 file changed, 82 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 89a772d..2dfd516 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1453,7 +1453,7 @@
vin-ldo9-10-supply = <&vdd_5v0_sys>;
vin-ldo11-supply = <&vdd_3v3_run>;
- sd0 {
+ vdd_cpu: sd0 {
regulator-name = "+VDD_CPU_AP";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1400000>;
@@ -1636,6 +1636,87 @@
non-removable;
};
+ dfll@0,70110000 {
+ status = "okay";
+ vdd_cpu-supply = <&vdd_cpu>;
+ nvidia,i2c-fs-rate = <400000>;
+ nvidia,pmic-i2c-address = <0x40>;
+ nvidia,pmic-i2c-voltage-register = <0x00>;
+
+ nvidia,pmic-voltage-table =
+ <0x1e 700000>,
+ <0x1f 710000>,
+ <0x20 720000>,
+ <0x21 730000>,
+ <0x22 740000>,
+ <0x23 750000>,
+ <0x24 760000>,
+ <0x25 770000>,
+ <0x26 780000>,
+ <0x27 790000>,
+ <0x28 800000>,
+ <0x29 810000>,
+ <0x2a 820000>,
+ <0x2b 830000>,
+ <0x2c 840000>,
+ <0x2d 850000>,
+ <0x2e 860000>,
+ <0x2f 870000>,
+ <0x30 880000>,
+ <0x31 890000>,
+ <0x32 900000>,
+ <0x33 910000>,
+ <0x34 920000>,
+ <0x35 930000>,
+ <0x36 940000>,
+ <0x37 950000>,
+ <0x38 960000>,
+ <0x39 970000>,
+ <0x3a 980000>,
+ <0x3b 990000>,
+ <0x3c 1000000>,
+ <0x3d 1010000>,
+ <0x3e 1020000>,
+ <0x3f 1030000>,
+ <0x40 1040000>,
+ <0x41 1050000>,
+ <0x42 1060000>,
+ <0x43 1070000>,
+ <0x44 1080000>,
+ <0x45 1090000>,
+ <0x46 1100000>,
+ <0x47 1110000>,
+ <0x48 1120000>,
+ <0x49 1130000>,
+ <0x4a 1140000>,
+ <0x4b 1150000>,
+ <0x4c 1160000>,
+ <0x4d 1170000>,
+ <0x4e 1180000>,
+ <0x4f 1190000>,
+ <0x50 1200000>,
+ <0x51 1210000>,
+ <0x52 1220000>,
+ <0x53 1230000>,
+ <0x54 1240000>,
+ <0x55 1250000>,
+ <0x56 1260000>,
+ <0x57 1270000>,
+ <0x58 1280000>,
+ <0x59 1290000>,
+ <0x5a 1300000>,
+ <0x5b 1310000>,
+ <0x5c 1320000>,
+ <0x5d 1330000>,
+ <0x5e 1340000>,
+ <0x5f 1350000>,
+ <0x60 1360000>,
+ <0x61 1370000>,
+ <0x62 1380000>,
+ <0x63 1390000>,
+ <0x64 1400000>;
+ };
+
ahub@0,70300000 {
i2s@0,70301100 {
status = "okay";
--
1.8.1.5
next prev parent reply other threads:[~2014-07-10 21:45 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-10 21:42 [PATCH 00/13] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 01/13] clk: tegra: Add binding for the Tegra124 DFLL clocksource Tuomas Tynkkynen
2014-07-11 16:28 ` Andrew Bresticker
2014-07-11 16:48 ` Tuomas Tynkkynen
2014-07-11 17:08 ` Andrew Bresticker
2014-07-11 17:21 ` Tuomas Tynkkynen
2014-07-14 8:38 ` Thierry Reding
2014-07-14 9:12 ` Mark Brown
2014-07-14 9:24 ` Thierry Reding
2014-07-14 10:22 ` Mark Brown
2014-07-15 20:23 ` Tuomas Tynkkynen
2014-07-15 22:52 ` Mark Brown
2014-07-16 8:01 ` Thierry Reding
2014-07-16 11:00 ` Mark Brown
2014-07-10 21:42 ` [PATCH 02/13] clk: tegra: Add library for the DFLL clock source (open-loop mode) Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 03/13] clk: tegra: Add closed loop support for the DFLL Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 04/13] clk: tegra: Add functions for parsing CVB tables Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 05/13] clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 06/13] clk: tegra: Add Tegra124 DFLL clocksource platform driver Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 07/13] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 08/13] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 09/13] ARM: tegra: Add the DFLL to Tegra124 device tree Tuomas Tynkkynen
2014-07-10 21:42 ` Tuomas Tynkkynen [this message]
2014-07-11 7:14 ` [PATCH 10/13] ARM: tegra: Enable the DFLL on the Jetson TK1 Mikko Perttunen
2014-07-10 21:42 ` [PATCH 11/13] cpufreq: tegra124: Add device tree bindings Tuomas Tynkkynen
2014-07-10 21:42 ` [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124 Tuomas Tynkkynen
2014-07-11 4:35 ` Viresh Kumar
2014-07-11 9:12 ` Peter De Schrijver
2014-07-11 9:14 ` Viresh Kumar
2014-07-11 14:57 ` Thierry Reding
2014-07-11 15:11 ` Tuomas Tynkkynen
2014-07-11 15:15 ` Thierry Reding
2014-07-11 15:29 ` Tuomas Tynkkynen
2014-07-11 16:33 ` Andrew Bresticker
2014-07-11 14:14 ` Tuomas Tynkkynen
2014-07-11 14:37 ` Viresh Kumar
2014-07-10 21:42 ` [PATCH 13/13] ARM: tegra: Add entries for cpufreq on Tegra124 Tuomas Tynkkynen
2014-07-11 15:32 ` [PATCH 00/13] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Mike Turquette
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