From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: linux-kernel@vger.kernel.org
Subject: [PATCH 24/25] clocksource: exynos_mct: Use readl_relaxed/writel_relaxed
Date: Wed, 23 Jul 2014 12:54:06 +0200 [thread overview]
Message-ID: <1406112847-26275-24-git-send-email-daniel.lezcano@linaro.org> (raw)
In-Reply-To: <1406112847-26275-1-git-send-email-daniel.lezcano@linaro.org>
From: Doug Anderson <dianders@chromium.org>
Using the __raw functions is discouraged. Update the file to
consistently use the proper functions.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/exynos_mct.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index ab51bf20a..2df03e2 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -94,7 +94,7 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
u32 mask;
u32 i;
- __raw_writel(value, reg_base + offset);
+ writel_relaxed(value, reg_base + offset);
if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
@@ -144,8 +144,8 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
/* Wait maximum 1 ms until written values are applied */
for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
- if (__raw_readl(reg_base + stat_addr) & mask) {
- __raw_writel(mask, reg_base + stat_addr);
+ if (readl_relaxed(reg_base + stat_addr) & mask) {
+ writel_relaxed(mask, reg_base + stat_addr);
return;
}
@@ -157,7 +157,7 @@ static void exynos4_mct_frc_start(void)
{
u32 reg;
- reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
@@ -165,12 +165,12 @@ static void exynos4_mct_frc_start(void)
static cycle_t notrace _exynos4_frc_read(void)
{
unsigned int lo, hi;
- u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
do {
hi = hi2;
- lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
- hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
+ hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
} while (hi != hi2);
return ((cycle_t)hi << 32) | lo;
@@ -225,7 +225,7 @@ static void exynos4_mct_comp0_stop(void)
{
unsigned int tcon;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -238,7 +238,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
unsigned int tcon;
cycle_t comp_cycle;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -327,7 +327,7 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
- tmp = __raw_readl(reg_base + offset);
+ tmp = readl_relaxed(reg_base + offset);
if (tmp & mask) {
tmp &= ~mask;
exynos4_mct_write(tmp, offset);
@@ -349,7 +349,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
/* enable MCT tick interrupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
- tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
+ tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
MCT_L_TCON_INTERVAL_MODE;
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -401,7 +401,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
exynos4_mct_tick_stop(mevt);
/* Clear the MCT tick interrupt */
- if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+ if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
return 1;
} else {
--
1.7.9.5
next prev parent reply other threads:[~2014-07-23 10:55 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-23 10:51 [PULL] clockevents changes for 3.17 Daniel Lezcano
2014-07-23 10:53 ` [PATCH 01/25] clocksource: sh_cmt: Drop support for legacy platform data Daniel Lezcano
2014-07-23 10:53 ` [PATCH 02/25] clocksource: sh_cmt: Replace global spinlock with a per-device spinlock Daniel Lezcano
2014-07-23 10:53 ` [PATCH 03/25] clocksource: sh_tmu: Drop support for legacy platform data Daniel Lezcano
2014-07-23 10:53 ` [PATCH 04/25] clocksource: sh_tmu: Replace global spinlock with a per-device spinlock Daniel Lezcano
2014-07-23 10:53 ` [PATCH 05/25] clocksource: sh_mtu2: Drop support for legacy platform data Daniel Lezcano
2014-07-23 10:53 ` [PATCH 06/25] clocksource: sh_mtu2: Replace global spinlock with a per-device spinlock Daniel Lezcano
2014-07-23 10:53 ` [PATCH 07/25] clocksource: shmobile: Remove unused sh_timer_config members Daniel Lezcano
2014-07-23 10:53 ` [PATCH 08/25] clocksource: sh_cmt: Add DT support Daniel Lezcano
2014-07-23 10:53 ` [PATCH 09/25] clocksource: sh_tmu: " Daniel Lezcano
2014-07-23 10:53 ` [PATCH 10/25] clocksource: sh_mtu2: " Daniel Lezcano
2014-07-23 10:53 ` [PATCH 11/25] clocksource: sh_mtu2: Tidy up Kconfig typo for MTU2 Daniel Lezcano
2014-07-23 10:53 ` [PATCH 12/25] of: Provide a function to request and map memory Daniel Lezcano
2014-07-23 10:53 ` [PATCH 13/25] clocksource: Add support for the Mediatek SoCs Daniel Lezcano
2014-07-23 10:53 ` [PATCH 14/25] dt-bindings: Add mtk-timer bindings Daniel Lezcano
2014-07-23 10:53 ` [PATCH 15/25] vendor-prefixes: Add prefix for Mediatek Inc Daniel Lezcano
2014-07-23 10:53 ` [PATCH 16/25] clocksource: Kconfig: Let EM_TIMER_STI depend on HAS_IOMEM Daniel Lezcano
2014-07-23 10:53 ` [PATCH 17/25] clocksource: sirf: Fix incorrect clock enable counter for timer Daniel Lezcano
2014-07-23 10:54 ` [PATCH 18/25] clocksource: clps711x: Add CLPS711X clocksource driver Daniel Lezcano
2014-07-23 10:54 ` [PATCH 19/25] clocksource: clps711x: Add DT bindings documentation Daniel Lezcano
2014-07-23 10:54 ` [PATCH 20/25] clocksource: pxa: Move PXA timer to clocksource framework Daniel Lezcano
2014-07-23 10:54 ` [PATCH 21/25] clocksource: pxa: Add device-tree support for PXA timer Daniel Lezcano
2014-07-23 10:54 ` [PATCH 22/25] ARM: pxa: Add CLKSRC_OF dependency Daniel Lezcano
2014-07-23 10:54 ` [PATCH 23/25] ARM: pxa: Add non device-tree timer link to clocksource Daniel Lezcano
2014-07-23 10:54 ` Daniel Lezcano [this message]
2014-07-23 10:54 ` [PATCH 25/25] clocksource: exynos_mct: Only use 32-bits where possible Daniel Lezcano
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