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b=lSRp6XtHyvtRo8E9z4PiIMZpYX3RfX9MelXeEy7L04ZdIB9HEg0cWTiVkA/jEqH9StfuHLk+cyyefuP/nVZ5+e7iR7+oBAfY665aJy5+0zThGgiHMt2l0Ts30rdythZU7KuBScakKKCY/i0tN7npmHraYG4bstDvWm1E4ruOFY4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com; Received: from CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) by CH5PR03MB7933.namprd03.prod.outlook.com (2603:10b6:610:20e::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.18; Thu, 5 Mar 2026 14:10:14 +0000 Received: from CH8PR03MB8275.namprd03.prod.outlook.com ([fe80::a70d:dc32:bba8:ce37]) by CH8PR03MB8275.namprd03.prod.outlook.com ([fe80::a70d:dc32:bba8:ce37%6]) with mapi id 15.20.9678.016; Thu, 5 Mar 2026 14:10:14 +0000 Message-ID: <14074526-5b43-457c-bf75-cef6d5088193@citrix.com> Date: Thu, 5 Mar 2026 14:10:10 +0000 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, mingo@redhat.com, stable@vger.kernel.org, tglx@kernel.org, x86@kernel.org, David Wang , lukelin@viacpu.com, brucechang@via-alliance.com, "TimGuo@zhaoxin.com" , cooperyan@zhaoxin.com, benjaminpan@viatech.com, TimGuo-oc@zhaoxin.com, QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com, "CobeChen@zhaoxin.com" Subject: Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600 To: Yao Zi , Tony W Wang-oc References: <20260228173704.62460-1-me@ziyao.cc> <70139192-54e5-4a4b-bc96-1fe3ec4f7a0b@zhaoxin.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: Content-Type: text/plain; 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During execution of FSGSBASE-related >> instructions, the hardware actually checks whether this MSR >> register's bit is set to determine whether to generate a #UD >> exception. >> When the CPU enters SMM mode and then returns via RSM, the CR4 >> register is restored but the value of CR4.FSGSBASE is not >> re-propagated to the MSR register. >> As a result, after enabling CR4.FSGSBASE, once the CPU goes >> through SMM mode, executing FSGSBASE-related instructions will >> trigger a #UD exception. > Thanks for confirming the issue and the explanation! > >> This issue exists only on ZX-C CPUs, which have two different >> CPU vendor IDs and distinct FMS values. The following patch can >> be used to identify ZX-C CPUs and properly handle this issue: > However, I agree with Andrew that a ucode update, if possible, would > be the preferred way of fixing the issue up. > >> --- a/arch/x86/kernel/cpu/centaur.c >> +++ b/arch/x86/kernel/cpu/centaur.c >> @@ -201,6 +201,11 @@ static void init_centaur(struct cpuinfo_x86 *c) >> set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); >> #endif >> >> + if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping >= 14) { > Are this condition and the one below in zhaoxin.c precise enough to > recognize all and only the affected ZX-C models, without mistaking > unaffected designs even from VIA? Please see also my concerns raised > previously[1]. > > Though I haven't tried yet, since reproduction of the problem requires > entrance to SMM at least once, it may be hard to detect the quirk by > executing rdfsbase and seeing whether it traps. So if the conditions are > precise enough and a microcode fix isn't appropriate, I'd like to stick > with CPUID matching in v2. > > David, Andrew, is it okay for you? Given the SMM observation, this cannot be probed for reliably, so will have to have some kind of model check. Ideally using the microcode revision matching infrastructure, assuming that fixed ucode can be produced. ~Andrew