From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754003AbaHLHD3 (ORCPT ); Tue, 12 Aug 2014 03:03:29 -0400 Received: from szxga01-in.huawei.com ([119.145.14.64]:42426 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753775AbaHLHDZ (ORCPT ); Tue, 12 Aug 2014 03:03:25 -0400 From: Yijing Wang To: Bjorn Helgaas CC: , Xinwei Hu , Wuyun , , Marc Zyngier , , Russell King , , , "Arnd Bergmann" , Thomas Gleixner , "H. Peter Anvin" , Konrad Rzeszutek Wilk , , Joerg Roedel , , , "Benjamin Herrenschmidt" , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Yijing Wang Subject: [RFC PATCH 19/20] tile/MSI: Use msi_chip instead of arch func to configure MSI/MSI-X Date: Tue, 12 Aug 2014 15:26:12 +0800 Message-ID: <1407828373-24322-20-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1407828373-24322-1-git-send-email-wangyijing@huawei.com> References: <1407828373-24322-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce a new struct msi_chip tile_msi_chip instead of weak arch functions to configure MSI/MSI-X. Signed-off-by: Yijing Wang --- arch/tile/kernel/pci_gx.c | 20 +++++++++++++++----- 1 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index e39f9c5..d1f308c 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -1485,7 +1485,7 @@ static struct irq_chip tilegx_msi_chip = { /* TBD: support set_affinity. */ }; -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +int tile_setup_msi_irq(struct device *dev, struct msi_desc *desc) { struct pci_controller *controller; gxio_trio_context_t *trio_context; @@ -1510,7 +1510,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) * Most PCIe endpoint devices do support 64-bit message addressing. */ if (desc->msi_attrib.is_64 == 0) { - dev_printk(KERN_INFO, &pdev->dev, + dev_printk(KERN_INFO, dev, "64-bit MSI message address not supported, " "falling back to legacy interrupts.\n"); @@ -1549,7 +1549,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) /* SQ regions are out, allocate from map mem regions. */ mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0); if (mem_map < 0) { - dev_printk(KERN_INFO, &pdev->dev, + dev_printk(KERN_INFO, dev, "%s Mem-Map alloc failure. " "Failed to initialize MSI interrupts. " "Falling back to legacy interrupts.\n", @@ -1580,7 +1580,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) mem_map, mem_map_base, mem_map_limit, trio_context->asid); if (ret < 0) { - dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n"); + dev_printk(KERN_INFO, dev, "HV MSI config failed.\n"); goto hv_msi_config_failure; } @@ -1604,7 +1604,17 @@ is_64_failure: return ret; } -void arch_teardown_msi_irq(unsigned int irq) +void tile_teardown_msi_irq(unsigned int irq) { irq_free_hwirq(irq); } + +struct msi_chip tile_msi_chip = { + .setup_irq = tile_setup_msi_irq, + .teardown_irq = tile_teardown_msi_irq, +}; + +struct msi_chip *arch_get_match_msi_chip(struct device *dev) +{ + return &tile_msi_chip; +} -- 1.7.1