From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753730AbaHNBR6 (ORCPT ); Wed, 13 Aug 2014 21:17:58 -0400 Received: from mga02.intel.com ([134.134.136.20]:65466 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752042AbaHNBR4 (ORCPT ); Wed, 13 Aug 2014 21:17:56 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,859,1400050800"; d="scan'208";a="587829265" From: Andi Kleen To: peterz@infradead.org Cc: linux-kernel@vger.kernel.org, mingo@kernel.org, eranian@google.com, Andi Kleen Subject: [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell Date: Wed, 13 Aug 2014 18:17:49 -0700 Message-Id: <1407979069-7121-6-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1407979069-7121-1-git-send-email-andi@firstfloor.org> References: <1407979069-7121-1-git-send-email-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen Use the newly added Broadwell cache event list for Haswell too. They are identical, but Haswell is very different from the Sandy Bridge list that was used previously. That fixes a wide range of mis-counting cache events. The prefetch events are gone now. They way the hardware counts them is very misleading (some prefetches included, others not), so it seemed best to leave them out. Signed-off-by: Andi Kleen --- arch/x86/kernel/cpu/perf_event_intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 66260e1..178ddc0 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2691,8 +2691,8 @@ __init int intel_pmu_init(void) case 63: /* Haswell Server */ case 69: /* Haswell ULT */ x86_pmu.late_ack = true; - memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); - memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); + memcpy(hw_cache_event_ids, bdw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); + memcpy(hw_cache_extra_regs, bdw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); intel_pmu_lbr_init_snb(); -- 1.9.3