From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754234AbaIHJkN (ORCPT ); Mon, 8 Sep 2014 05:40:13 -0400 Received: from mail-bn1on0063.outbound.protection.outlook.com ([157.56.110.63]:62000 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754175AbaIHJkF (ORCPT ); Mon, 8 Sep 2014 05:40:05 -0400 From: Ley Foon Tan To: , , CC: Ley Foon Tan , , Subject: [PATCH v3 24/29] nios2: Nios2 registers Date: Mon, 8 Sep 2014 17:22:35 +0800 Message-ID: <1410168160-3624-25-git-send-email-lftan@altera.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1410168160-3624-1-git-send-email-lftan@altera.com> References: <1410168160-3624-1-git-send-email-lftan@altera.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.227;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009017)(6009001)(199003)(189002)(92726001)(2201001)(106466001)(77096002)(102836001)(87286001)(107046002)(93916002)(50226001)(4396001)(105596002)(88136002)(85852003)(83072002)(90102001)(86362001)(92566001)(87936001)(99396002)(229853001)(89996001)(81542001)(50986999)(77156001)(77982001)(85306004)(36756003)(95666004)(21056001)(76482001)(15975445006)(20776003)(74662001)(31966008)(74502001)(80022001)(46102001)(6806004)(47776003)(15202345003)(33646002)(44976005)(97736003)(83322001)(68736004)(79102001)(76176999)(104166001)(81342001)(84676001)(50466002)(62966002)(19580405001)(19580395003)(48376002)(42186005)(2004002);DIR:OUT;SFP:1101;SCL:1;SRVR:BN1PR0301MB0642;H:sj-itexedge03.altera.priv.altera.com;FPR:;MLV:sfv;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 03283976A6 Authentication-Results: spf=softfail (sender IP is 66.35.236.227) smtp.mailfrom=lftan@altera.com; X-OriginatorOrg: altera.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This file contains constants for the instruction macros, cpu registers, fields and bits. Signed-off-by: Ley Foon Tan --- arch/nios2/include/asm/registers.h | 71 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 arch/nios2/include/asm/registers.h diff --git a/arch/nios2/include/asm/registers.h b/arch/nios2/include/asm/registers.h new file mode 100644 index 0000000..615bce1 --- /dev/null +++ b/arch/nios2/include/asm/registers.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2011 Tobias Klauser + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#ifndef _ASM_NIOS2_REGISTERS_H +#define _ASM_NIOS2_REGISTERS_H + +#ifndef __ASSEMBLY__ +#include +#endif + +/* control register numbers */ +#define CTL_STATUS 0 +#define CTL_ESTATUS 1 +#define CTL_BSTATUS 2 +#define CTL_IENABLE 3 +#define CTL_IPENDING 4 +#define CTL_CPUID 5 +#define CTL_RSV1 6 +#define CTL_EXCEPTION 7 +#define CTL_PTEADDR 8 +#define CTL_TLBACC 9 +#define CTL_TLBMISC 10 +#define CTL_RSV2 11 +#define CTL_BADADDR 12 +#define CTL_CONFIG 13 +#define CTL_MPUBASE 14 +#define CTL_MPUACC 15 + +/* access control registers using GCC builtins */ +#define RDCTL(r) __builtin_rdctl(r) +#define WRCTL(r, v) __builtin_wrctl(r, v) + +/* status register bits */ +#define STATUS_PIE (1 << 0) /* processor interrupt enable */ +#define STATUS_U (1 << 1) /* user mode */ +#define STATUS_EH (1 << 2) /* Exception mode */ + +/* estatus register bits */ +#define ESTATUS_EPIE (1 << 0) /* processor interrupt enable */ +#define ESTATUS_EU (1 << 1) /* user mode */ +#define ESTATUS_EH (1 << 2) /* Exception mode */ + +/* tlbmisc register bits */ +#define TLBMISC_PID_SHIFT 4 +#ifndef __ASSEMBLY__ +#define TLBMISC_PID_MASK ((1UL << cpuinfo.tlb_pid_num_bits) - 1) +#endif +#define TLBMISC_WAY_MASK 0xf +#define TLBMISC_WAY_SHIFT 20 + +#define TLBMISC_PID (TLBMISC_PID_MASK << TLBMISC_PID_SHIFT) /* TLB PID */ +#define TLBMISC_WE (1 << 18) /* TLB write enable */ +#define TLBMISC_RD (1 << 19) /* TLB read */ +#define TLBMISC_WAY (TLBMISC_WAY_MASK << TLBMISC_WAY_SHIFT) /* TLB way */ + +#endif /* _ASM_NIOS2_REGISTERS_H */ -- 1.8.2.1