From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752525AbaIJKUz (ORCPT ); Wed, 10 Sep 2014 06:20:55 -0400 Received: from bhuna.collabora.co.uk ([93.93.135.160]:35328 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752368AbaIJKU1 (ORCPT ); Wed, 10 Sep 2014 06:20:27 -0400 From: Javier Martinez Canillas To: Kukjin Kim Cc: Doug Anderson , Olof Johansson , Mark Brown , Naveen Krishna Chatradhi , Rahul Sharma , Andreas Faerber , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Vivek Gautam , Javier Martinez Canillas Subject: [PATCH v3 6/7] ARM: dts: Set i2c7 clock at 400kHz for Peach boards Date: Wed, 10 Sep 2014 12:19:50 +0200 Message-Id: <1410344391-5675-7-git-send-email-javier.martinez@collabora.co.uk> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1410344391-5675-1-git-send-email-javier.martinez@collabora.co.uk> References: <1410344391-5675-1-git-send-email-javier.martinez@collabora.co.uk> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The downstream ChromeOS 3.8 kernel sets the clock frequency for the I2C bus 7 at 400kHz. Do the same change in mainline. Suggested-by: Doug Anderson Signed-off-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 1 + arch/arm/boot/dts/exynos5800-peach-pi.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index b8fea56..f247709 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -489,6 +489,7 @@ &hsi2c_7 { status = "okay"; + clock-frequency = <400000>; max98090: codec@10 { compatible = "maxim,max98090"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 17537f0..88b3544 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -487,6 +487,7 @@ &hsi2c_7 { status = "okay"; + clock-frequency = <400000>; max98091: codec@10 { compatible = "maxim,max98091"; -- 2.1.0