From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752914AbaIYHvi (ORCPT ); Thu, 25 Sep 2014 03:51:38 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:40308 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752586AbaIYHvZ (ORCPT ); Thu, 25 Sep 2014 03:51:25 -0400 From: Kever Yang To: heiko@sntech.de, Mike Turquette Cc: dianders@chromium.org, sonnyrao@chromium.org, addy.ke@rock-chips.com, cf@rock-chips.com, xjq@rock-chips.com, hj@rock-chips.com, huangtao@rock-chips.com, linux-rockchip@lists.infradead.org, Kever Yang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] clk: rockchip: add clock node in PD_VIDEO Date: Thu, 25 Sep 2014 15:48:47 +0800 Message-Id: <1411631328-14973-4-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411631328-14973-1-git-send-email-kever.yang@rock-chips.com> References: <1411631328-14973-1-git-send-email-kever.yang@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add the clock node in PD_VIDEO Signed-off-by: Kever Yang Reviewed-by: Heiko Stuebner --- Changes in v3: - add a fix factor - introduce a virtual node to implement the clock struct Changes in v2: - split out the patch drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index dd204cb..d466814 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -296,6 +296,20 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 11, GFLAGS), + /* + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, + * so we ignore the mux and make clocks nodes as following, + */ + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(9), 0, GFLAGS), + /* + * We introduce a virtul node of hclk_vodec_pre_v to split one clock + * sturct with a gate and a fix divider into two node in software. + */ + GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(3), 10, GFLAGS), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, + RK3288_CLKGATE_CON(9), 1, GFLAGS), COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, @@ -711,6 +725,12 @@ static void __init rk3288_clk_init(struct device_node *np) pr_warn("%s: could not register clock usb480m: %ld\n", __func__, PTR_ERR(clk)); + clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", + "hclk_vcodec_pre_v", 0, 1, 4); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", + __func__, PTR_ERR(clk)); + rockchip_clk_register_plls(rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), RK3288_GRF_SOC_STATUS); -- 1.9.1