From: Yijing Wang <wangyijing@huawei.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Xinwei Hu <huxinwei@huawei.com>, Wuyun <wuyun.wu@huawei.com>,
<linux-arm-kernel@lists.infradead.org>,
Russell King <linux@arm.linux.org.uk>,
Thomas Gleixner <tglx@linutronix.de>,
"Thierry Reding" <thierry.reding@gmail.com>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Yijing Wang <wangyijing@huawei.com>
Subject: [PATCH 08/10] PCI: xilinx: Save MSI controller in pci_sys_data
Date: Mon, 27 Oct 2014 15:48:45 +0800 [thread overview]
Message-ID: <1414396127-30023-9-git-send-email-wangyijing@huawei.com> (raw)
In-Reply-To: <1414396127-30023-1-git-send-email-wangyijing@huawei.com>
Save MSI controller in pci_sys_data instead of
assigning MSI controller pointer to every pci bus
in .add_bus().
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
drivers/pci/host/pcie-xilinx.c | 19 ++++---------------
1 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index ce19133..5a3e5a0 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -431,20 +431,6 @@ static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
}
-/**
- * xilinx_pcie_add_bus - Add MSI chip info to PCIe bus
- * @bus: PCIe bus
- */
-static void xilinx_pcie_add_bus(struct pci_bus *bus)
-{
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
-
- xilinx_pcie_msi_controller.dev = port->dev;
- bus->msi = &xilinx_pcie_msi_controller;
- }
-}
-
/* INTx Functions */
/**
@@ -924,10 +910,13 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
.private_data = (void **)&port,
.setup = xilinx_pcie_setup,
.map_irq = of_irq_parse_and_map_pci,
- .add_bus = xilinx_pcie_add_bus,
.scan = xilinx_pcie_scan_bus,
.ops = &xilinx_pcie_ops,
};
+#ifdef CONFIG_PCI_MSI
+ xilinx_pcie_msi_controller.dev = port->dev;
+ hw.msi_ctrl = &xilinx_pcie_msi_controller;
+#endif
pci_common_init_dev(dev, &hw);
return 0;
--
1.7.1
next prev parent reply other threads:[~2014-10-27 7:10 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-27 7:48 [PATCH 00/10] Save MSI chip " Yijing Wang
2014-10-27 7:48 ` [PATCH 01/10] MSI: Rename msi_chip to msi_controller for better readability Yijing Wang
2014-10-27 7:48 ` [PATCH 02/10] PCI/MSI: Introduce weak pcibios_msi_controller() Yijing Wang
2014-10-27 7:48 ` [PATCH 03/10] arm/MSI: Save MSI controller in pci_sys_data Yijing Wang
2014-10-27 7:48 ` [PATCH 04/10] PCI: tegra: " Yijing Wang
2014-10-27 7:48 ` [PATCH 05/10] PCI: designware: " Yijing Wang
2014-10-27 7:48 ` [PATCH 06/10] PCI: rcar: " Yijing Wang
2014-10-27 7:48 ` [PATCH 07/10] PCI: mvebu: " Yijing Wang
2014-10-27 7:48 ` Yijing Wang [this message]
2014-10-27 7:48 ` [PATCH 09/10] arm/PCI: Clean unused pcibios_add_bus() and pcibios_remove_bus() Yijing Wang
2014-10-27 7:48 ` [PATCH 10/10] PCI/MSI: Remove useless bus->msi assignment Yijing Wang
2014-11-12 4:24 ` Bjorn Helgaas
2014-11-12 5:54 ` Yijing Wang
2014-11-12 4:23 ` [PATCH 00/10] Save MSI chip in pci_sys_data Bjorn Helgaas
2014-11-17 2:59 ` Bjorn Helgaas
2014-11-17 9:38 ` Thomas Gleixner
2014-11-17 16:54 ` Bjorn Helgaas
2014-11-17 21:02 ` Thomas Gleixner
2014-11-17 21:27 ` Bjorn Helgaas
2014-11-17 21:31 ` Thomas Gleixner
2014-11-18 17:53 ` Marc Zyngier
2014-11-21 17:20 ` Bjorn Helgaas
2014-11-22 2:58 ` Yijing Wang
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