From: Kevin Cernekee <cernekee@gmail.com>
To: ralf@linux-mips.org
Cc: f.fainelli@gmail.com, jfraser@broadcom.com, dtor@chromium.org,
tglx@linutronix.de, jason@lakedaemon.net,
linux-mips@linux-mips.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH V2 15/22] MIPS: BMIPS: Let each platform customize the CPU1 IRQ mask
Date: Sat, 15 Nov 2014 16:17:39 -0800 [thread overview]
Message-ID: <1416097066-20452-16-git-send-email-cernekee@gmail.com> (raw)
In-Reply-To: <1416097066-20452-1-git-send-email-cernekee@gmail.com>
On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1
input, generating spurious IRQs. In this case we want the platform code
to be able to mask it off.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index cbacceb..30939b0 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -84,6 +84,7 @@ extern char bmips_smp_int_vec_end;
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
extern cpumask_t bmips_booted_mask;
+extern unsigned long bmips_tp1_irqs;
extern void bmips_ebase_setup(void);
extern asmlinkage void plat_wired_tlb_setup(void);
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 162391d..b8bd934 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -43,6 +43,7 @@ static int __maybe_unused max_cpus = 1;
int bmips_smp_enabled = 1;
int bmips_cpu_offset;
cpumask_t bmips_booted_mask;
+unsigned long bmips_tp1_irqs = IE_IRQ1;
#define RESET_FROM_KSEG0 0x80080800
#define RESET_FROM_KSEG1 0xa0080800
@@ -257,7 +258,7 @@ static void bmips_smp_finish(void)
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
irq_enable_hazard();
- set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
+ set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
irq_enable_hazard();
}
@@ -387,7 +388,8 @@ void __ref play_dead(void)
* IRQ handlers; this clears ST0_IE and returns immediately.
*/
clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
- change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
+ change_c0_status(
+ IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
irq_disable_hazard();
--
2.1.1
next prev parent reply other threads:[~2014-11-16 0:19 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-16 0:17 [PATCH V2 00/22] Multiplatform BMIPS kernel Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 01/22] irqchip: Update docs regarding irq_domain_add_tree() Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 02/22] irqchip: brcmstb-l2: fix error handling of irq_of_parse_and_map Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 03/22] irqchip: bcm7120-l2: " Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 04/22] irqchip: bcm7120-l2: Refactor driver for arbitrary IRQEN/IRQSTAT offsets Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 05/22] irqchip: bcm7120-l2: Change DT binding to allow non-contiguous IRQEN/IRQSTAT Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 06/22] irqchip: Add new driver for BCM7038-style level 1 interrupt controllers Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 07/22] MIPS: BMIPS: Fix ".previous without corresponding .section" warnings Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 08/22] MIPS: BMIPS: Align secondary boot sequence with latest firmware releases Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 09/22] MIPS: BMIPS: Introduce helper function to change the reset vector Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 10/22] MIPS: BMIPS: Allow BMIPS3300 to utilize SMP ebase relocation code Kevin Cernekee
2014-11-20 23:40 ` Ralf Baechle
2014-11-16 0:17 ` [PATCH V2 11/22] MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPU Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 12/22] MIPS: BMIPS: Explicitly configure reset vectors prior to secondary boot Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 13/22] MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizes Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 14/22] MIPS: BMIPS: Fix L1_CACHE_SHIFT when BMIPS5000 is selected Kevin Cernekee
2014-11-16 0:17 ` Kevin Cernekee [this message]
2014-11-16 0:17 ` [PATCH V2 16/22] MIPS: BMIPS: Add special cache handling in c-r4k.c Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 17/22] MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind) Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 18/22] MIPS: Create a helper function for DT setup Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 19/22] Documentation: DT: Add "mti" vendor prefix Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 20/22] MAINTAINERS: Add entry for bcm63xx/bcm33xx UDC gadget driver Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 21/22] MAINTAINERS: Add entry for BMIPS multiplatform kernel Kevin Cernekee
2014-11-16 0:17 ` [PATCH V2 22/22] MIPS: Add multiplatform BMIPS target Kevin Cernekee
2014-11-16 21:24 ` Arnd Bergmann
2014-11-16 22:12 ` Kevin Cernekee
2014-11-17 12:16 ` Arnd Bergmann
2014-11-17 14:52 ` Jonas Gorski
2014-11-17 16:13 ` Arnd Bergmann
2014-11-17 17:19 ` Kevin Cernekee
2014-11-17 18:55 ` Arnd Bergmann
2014-11-17 19:47 ` Kevin Cernekee
2014-11-17 20:33 ` Arnd Bergmann
2014-11-17 21:57 ` Kevin Cernekee
2014-11-18 10:15 ` Arnd Bergmann
2014-11-17 17:01 ` Kevin Cernekee
2014-11-17 18:46 ` Arnd Bergmann
2014-11-17 19:39 ` Kevin Cernekee
2014-11-17 20:40 ` Arnd Bergmann
2014-11-17 21:21 ` Kevin Cernekee
2014-11-17 23:06 ` Jonas Gorski
2014-11-18 10:19 ` Arnd Bergmann
2014-11-17 14:44 ` Jonas Gorski
2014-11-17 20:35 ` Kevin Cernekee
2014-11-17 23:00 ` Jonas Gorski
2014-11-20 3:04 ` [PATCH V2 00/22] Multiplatform BMIPS kernel Brian Norris
2014-11-20 3:55 ` Kevin Cernekee
2014-11-20 18:09 ` Florian Fainelli
2014-11-20 20:13 ` Kevin Cernekee
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