From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752246AbaLDHPz (ORCPT ); Thu, 4 Dec 2014 02:15:55 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:49114 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750992AbaLDHPx (ORCPT ); Thu, 4 Dec 2014 02:15:53 -0500 X-Listener-Flag: 11101 Subject: Re: [PATCH v2 0/4] clk: mediatek: Add common clock support for Mediatek MT8135. From: James Liao To: Rob Herring , Matthias Brugger , Mike Turquette CC: srv_heupstream , Sascha Hauer , Eddie Huang =?euc-kr?Q?=28=FC=DC=F2=AA=CB=F8=29?= , HenryC Chen =?iso-2022-jp?Q?=28=1B=24BDD7z9k=1B=28B=29?= , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Catalin Marinas , Vladimir Murzin , Ashwin Chaugule , Yingjoe Chen =?iso-2022-jp?Q?=28=1B=24BDD1Q=3D=27=1B=28B=29?= , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" In-Reply-To: <1417675942-10502-1-git-send-email-jamesjj.liao@mediatek.com> References: <1417675942-10502-1-git-send-email-jamesjj.liao@mediatek.com> Content-Type: text/plain; charset="us-ascii" Date: Thu, 4 Dec 2014 15:15:49 +0800 Message-ID: <1417677349.31427.26.camel@mtksdaap41> MIME-Version: 1.0 X-Mailer: Evolution 2.28.3 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, 2014-12-04 at 14:52 +0800, James Liao wrote: > This patchset contains the initial common clock support for Mediatek SoCs. > Mediatek SoC's clock architecture comprises of various PLLs, dividers, > muxes and clock gates. > > This patchset also contains a basic clock support for Mediatek MT8135. > > This driver is based on 3.18-rc1 + MT8135 basic support. > Changein v2: - Re-ordered patchset. Fold include/dt-bindings and DT document in 1st patch.