From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752857AbaL3Dfx (ORCPT ); Mon, 29 Dec 2014 22:35:53 -0500 Received: from mail-bl2on0145.outbound.protection.outlook.com ([65.55.169.145]:4514 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752057AbaL3DaW (ORCPT ); Mon, 29 Dec 2014 22:30:22 -0500 From: Liu Ying To: CC: , , , , , , , , , , , , Subject: [PATCH RFC v7 06/21] ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock Date: Tue, 30 Dec 2014 11:33:56 +0800 Message-ID: <1419910451-15268-7-git-send-email-Ying.Liu@freescale.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1419910451-15268-1-git-send-email-Ying.Liu@freescale.com> References: <1419910451-15268-1-git-send-email-Ying.Liu@freescale.com> X-EOPAttributedMessage: 0 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Ying.Liu@freescale.com; X-Forefront-Antispam-Report: CIP:192.88.168.50;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(339900001)(189002)(199003)(92566001)(120916001)(99396003)(105606002)(2351001)(89996001)(110136001)(107046002)(106466001)(46102003)(36756003)(86362001)(229853001)(84676001)(6806004)(87936001)(50986999)(21056001)(77156002)(62966003)(64706001)(47776003)(19580405001)(104016003)(76176999)(85426001)(48376002)(77096005)(97736003)(31966008)(2950100001)(50226001)(68736005)(19580395003)(20776003)(50466002)(4396001)(32563001)(217873001);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR0301MB0632;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;MLV:sfv;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0632; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004);SRVR:BY2PR0301MB0632; X-Forefront-PRVS: 04410E544A X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0632; X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2014 03:30:17.1534 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;Ip=[192.88.168.50] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR0301MB0632 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr clock's parent should be the video_27m clock. The i.MX6DL reference manual has the same statement. This patch changes the hdmi_isfr clock's parent from the pll3_pfd1_540m clock to the video_27m clock. Suggested-by: Philipp Zabel Signed-off-by: Liu Ying --- v6->v7: * None. v5->v6: * None. v4->v5: * None. v3->v4: * None. v2->v3: * Newly introduced in v3. arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 9470df3..f19472a 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -401,7 +401,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); - clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); + clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); -- 2.1.0