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Bottomley" , "Martin K. Petersen" , Sai Krishna Potthuri , Ajay Neeli , Manivannan Sadhasivam , Pedro Sousa , Adrian Hunter , Can Guo , Asutosh Das Cc: imx@lists.linux.dev, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, clizzi@redhat.com, aruizrui@redhat.com, eballetb@redhat.com, echanude@redhat.com, Frank Li References: <20261103133215.1385823-1-larisa.grigore@oss.nxp.com> <20261103133215.1385823-11-larisa.grigore@oss.nxp.com> <444b8e4d-948a-48de-b40e-74246b849842@acm.org> Content-Language: en-US From: Larisa Ileana Grigore In-Reply-To: <444b8e4d-948a-48de-b40e-74246b849842@acm.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR2P281CA0012.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a::22) To GV2PR04MB12558.eurprd04.prod.outlook.com (2603:10a6:150:368::10) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB12558:EE_|AS8PR04MB9206:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d259e9a-e48e-433b-b688-08df423a3d2f X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|23010399003|19092799006|366016|921020|10067099003|56012099006|4143699003|11063799006|261021123027099003|261026121527099003|261022105027099003|261026140227099003|261022075727099003|261022115727099003|261028144727099003|261009223027099003|18002099003|22082099003; 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Since all S32N7 variants use the same vops callbacks >   (or vops can be embedded in struct s32n7_soc_data and recovered via >   container_of(hba->vops, ...)), one lookup suffices. Will be fixed in v11. > * ufs_s32n7_link_startup_post_change() still open-codes a local-only >   subset of ufshcd_dwc_connection_setup() (setting N_DEVICEID = 0 >   without N_DEVICEID_VALID, and skipping peer attributes). The v10 >   commit message states this "follows the Synopsys recommended >   sequence", but still does not explain why >   ufshcd_dwc_connection_setup() (used by ufs-amd-versal2.c) cannot be >   used on S32N79. > After re-checking the recommended S32N79 sequence, v11 moves the local N_DeviceID write back before link startup, as it was in the initial version of the driver. After link startup, only the local CPort 0 is touched (T_CPortFlags and T_ConnectionState). So the S32N79 sequence is not a subset of ufshcd_dwc_connection_setup(): the two sequences program different settings. The S32N79 sequence does not write N_DeviceID_valid or any peer attribute, so the values brought up by the controller are kept (host N_DeviceID_valid = 1, device T_PeerDeviceID = 0). The generic helper sets the host N_DeviceID_valid to 0 and the device T_PeerDeviceID to 1. > Other issues: > * Back-to-back writes to SCM_STATUS: ufs_s32n7_link_startup_pre_change() > performs two consecutive posted writel() calls to ufs->reg_scm + > SCM_STATUS (SCM_STATUS_PHY_RESET(1) immediately followed by > SCM_STATUS_PHY_RESET(1) | SCM_STATUS_SRAM_BYPASS(1)) with no readback or > delay in between. Either the first write is redundant, or if the > hardware requires observing SRAM_BYPASS = 0 while PHY_RESET = 1, a > readback/delay is missing and should be documented. The first write is not redundant: PRE_CHANGE also runs on host reset and error recovery, where the PHY may still be running, so it first puts the PHY back into reset; the RM requires no delay or readback between the two writes, the comment will be updated. > * Magic hex constants for shared DWC M-PHY bitfields: > s32n79_reset_config, s32n79_calib_mphy_disabled, > s32n79_calib_mphy_enabled, and pwr_change_phy_regs use raw hex values > (0x8A for CBREFCLKCTRL2 even though ufshcd-dwc.h already defines > CBREFREFCLK_GATE_OVR_EN, plus 0x4, 0x100, 0xc, 0x8). ufs-amd-versal2.c > already defines MPHY_FAST_RX_AFE_CAL, MPHY_FW_CALIB_CFG_VAL, > MPHY_RX_OVRD_EN, and MPHY_RX_OVRD_VAL for these same registers—moving > those bit macros to ufshcd-dwc.h would avoid magic numbers. Will be replaced in v11. Thanks, Larisa