From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755761AbbAFRMH (ORCPT ); Tue, 6 Jan 2015 12:12:07 -0500 Received: from mail-by2on0095.outbound.protection.outlook.com ([207.46.100.95]:31119 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755470AbbAFRLq (ORCPT ); Tue, 6 Jan 2015 12:11:46 -0500 From: Graham Moore To: CC: David Woodhouse , Brian Norris , , Alan Tull , Dinh Nguyen , Yves Vandervennet , Ezequiel Garcia , Graham Moore Subject: [PATCH V2 2/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver. Date: Tue, 6 Jan 2015 11:08:13 -0600 Message-ID: <1420564094-1086-2-git-send-email-grmoore@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1420564094-1086-1-git-send-email-grmoore@opensource.altera.com> References: <1420564094-1086-1-git-send-email-grmoore@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BLUPR05CA0055.namprd05.prod.outlook.com (10.141.20.25) To BL2PR03MB436.namprd03.prod.outlook.com (10.141.92.26) Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=grmoore@opensource.altera.com; X-DmarcAction: None X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(3005003);SRVR:BL2PR03MB436; X-Forefront-PRVS: 0448A97BF2 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(6009001)(199003)(189002)(110136001)(77156002)(87976001)(105586002)(40100003)(47776003)(21056001)(69596002)(97736003)(20776003)(120916001)(66066001)(107046002)(89996001)(46102003)(2351001)(19580395003)(99396003)(77096005)(68736005)(53416004)(76176999)(50986999)(551934003)(4396001)(106356001)(62966003)(122386002)(42186005)(64706001)(19580405001)(31966008)(81156004)(50466002)(86362001)(229853001)(92566001)(50226001)(33646002)(2950100001)(48376002);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2PR03MB436;H:lava-test-server.altera.com;FPR:;SPF:None;MLV:sfv;PTR:InfoNoRecords;A:0;MX:1;LANG:en; X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2015 17:11:42.4637 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB436 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Graham Moore --- .../devicetree/bindings/mtd/cadence_quadspi.txt | 50 ++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/cadence_quadspi.txt diff --git a/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt new file mode 100644 index 0000000..3a8ea1c --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt @@ -0,0 +1,50 @@ +* Cadence Quad SPI controller + +Required properties: +- compatible : Should be "cdns,qspi-nor". +- reg : Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the QSPI Controller data area. +- interrupts : Unit interrupt specifier for the controller interrupt. +- clocks : phandle to the Quad SPI clock. +- ext-decoder : Value of 0 means no external chipselect decoder is + connected, 1 means there is an external chipselect decoder connected. +- fifo-depth : Size of the data FIFO in words. +- bus-num : Number of the SPI bus to which the controller is connected. + +Optional subnodes: +Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional +custom properties: +- cdns,page-size : Size, in bytes, of the device's write page +- cdns,block-size : Size of the device's erase block +- cdns,read-delay : Selay for read capture logic, in clock cycles +- cdns,tshsl-ns : Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. +- cdns,tsd2d-ns : Delay in master reference clocks between one chip select being de-activated and the activation of another. +- cdns,tchsh-ns : Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (qspi_n_ss_out). +- cdns,tslch-ns : Delay in master reference clocks between setting qspi_n_ss_out low and first bit transfer. + +Example: + + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + ext-decoder = <0>; + fifo-depth = <128>; + + flash0: n25q00@0 { + ... + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + } + } -- 1.7.9.5