From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752488AbbANHQi (ORCPT ); Wed, 14 Jan 2015 02:16:38 -0500 Received: from mail-bl2on0084.outbound.protection.outlook.com ([65.55.169.84]:23184 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750964AbbANHQh (ORCPT ); Wed, 14 Jan 2015 02:16:37 -0500 X-Greylist: delayed 894 seconds by postgrey-1.27 at vger.kernel.org; Wed, 14 Jan 2015 02:16:36 EST From: Hao Liang To: , CC: , , , , "Hao Liang" Subject: [PATCH] BLACKFIN MEDIA DRIVER: rewrite the blackfin style of read/write into common style Date: Wed, 14 Jan 2015 14:57:33 +0800 Message-ID: <1421218653-16165-1-git-send-email-hliang1025@gmail.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Matching-Connectors: 130656924998039210;(52f37747-95c3-483a-bd05-08d153b03fac);() Authentication-Results: spf=softfail (sender IP is 137.71.25.57) smtp.mailfrom=hliang1025@gmail.com; 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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2015 07:01:39.3671 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;Ip=[137.71.25.57] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB0746 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Hao Liang --- drivers/media/platform/blackfin/ppi.c | 72 ++++++++++++++++----------------- 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/drivers/media/platform/blackfin/ppi.c b/drivers/media/platform/blackfin/ppi.c index cff63e5..de4b5c7 100644 --- a/drivers/media/platform/blackfin/ppi.c +++ b/drivers/media/platform/blackfin/ppi.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -59,10 +60,10 @@ static irqreturn_t ppi_irq_err(int irq, void *dev_id) /* register on bf561 is cleared when read * others are W1C */ - status = bfin_read16(®->status); + status = readw(®->status); if (status & 0x3000) ppi->err = true; - bfin_write16(®->status, 0xff00); + writew(0xff00, ®->status); break; } case PPI_TYPE_EPPI: @@ -70,10 +71,10 @@ static irqreturn_t ppi_irq_err(int irq, void *dev_id) struct bfin_eppi_regs *reg = info->base; unsigned short status; - status = bfin_read16(®->status); + status = readw(®->status); if (status & 0x2) ppi->err = true; - bfin_write16(®->status, 0xffff); + writew(0xffff, ®->status); break; } case PPI_TYPE_EPPI3: @@ -81,10 +82,10 @@ static irqreturn_t ppi_irq_err(int irq, void *dev_id) struct bfin_eppi3_regs *reg = info->base; unsigned long stat; - stat = bfin_read32(®->stat); + stat = readl(®->stat); if (stat & 0x2) ppi->err = true; - bfin_write32(®->stat, 0xc0ff); + writel(0xc0ff, ®->stat); break; } default: @@ -139,26 +140,25 @@ static int ppi_start(struct ppi_if *ppi) case PPI_TYPE_PPI: { struct bfin_ppi_regs *reg = info->base; - bfin_write16(®->control, ppi->ppi_control); + writew(ppi->ppi_control, ®->control); break; } case PPI_TYPE_EPPI: { struct bfin_eppi_regs *reg = info->base; - bfin_write32(®->control, ppi->ppi_control); + writel(ppi->ppi_control, ®->control); break; } case PPI_TYPE_EPPI3: { struct bfin_eppi3_regs *reg = info->base; - bfin_write32(®->ctl, ppi->ppi_control); + writel(ppi->ppi_control, ®->ctl); break; } default: return -EINVAL; } - SSYNC(); return 0; } @@ -172,19 +172,19 @@ static int ppi_stop(struct ppi_if *ppi) case PPI_TYPE_PPI: { struct bfin_ppi_regs *reg = info->base; - bfin_write16(®->control, ppi->ppi_control); + writew(ppi->ppi_control, ®->control); break; } case PPI_TYPE_EPPI: { struct bfin_eppi_regs *reg = info->base; - bfin_write32(®->control, ppi->ppi_control); + writel(ppi->ppi_control, ®->control); break; } case PPI_TYPE_EPPI3: { struct bfin_eppi3_regs *reg = info->base; - bfin_write32(®->ctl, ppi->ppi_control); + writel(ppi->ppi_control, ®->ctl); break; } default: @@ -195,7 +195,6 @@ static int ppi_stop(struct ppi_if *ppi) clear_dma_irqstat(info->dma_ch); disable_dma(info->dma_ch); - SSYNC(); return 0; } @@ -242,9 +241,9 @@ static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params) if (params->ppi_control & DMA32) dma32 = 1; - bfin_write16(®->control, ppi->ppi_control); - bfin_write16(®->count, samples_per_line - 1); - bfin_write16(®->frame, params->frame); + writew(ppi->ppi_control, ®->control); + writew(samples_per_line - 1, ®->count); + writew(params->frame, ®->frame); break; } case PPI_TYPE_EPPI: @@ -255,13 +254,13 @@ static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params) || (params->ppi_control & 0x38000) > DLEN_16) dma32 = 1; - bfin_write32(®->control, ppi->ppi_control); - bfin_write16(®->line, samples_per_line); - bfin_write16(®->frame, params->frame); - bfin_write16(®->hdelay, hdelay); - bfin_write16(®->vdelay, params->vdelay); - bfin_write16(®->hcount, hcount); - bfin_write16(®->vcount, params->height); + writel(ppi->ppi_control, ®->control); + writew(samples_per_line, ®->line); + writew(params->frame, ®->frame); + writew(hdelay, ®->hdelay); + writew(params->vdelay, ®->vdelay); + writew(hcount, ®->hcount); + writew(params->height, ®->vcount); break; } case PPI_TYPE_EPPI3: @@ -272,15 +271,15 @@ static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params) || (params->ppi_control & 0x70000) > DLEN_16) dma32 = 1; - bfin_write32(®->ctl, ppi->ppi_control); - bfin_write32(®->line, samples_per_line); - bfin_write32(®->frame, params->frame); - bfin_write32(®->hdly, hdelay); - bfin_write32(®->vdly, params->vdelay); - bfin_write32(®->hcnt, hcount); - bfin_write32(®->vcnt, params->height); + writel(ppi->ppi_control, ®->ctl); + writel(samples_per_line, ®->line); + writel(params->frame, ®->frame); + writel(hdelay, ®->hdly); + writel(params->vdelay, ®->vdly); + writel(hcount, ®->hcnt); + writel(params->height, ®->vcnt); if (params->int_mask) - bfin_write32(®->imsk, params->int_mask & 0xFF); + writel(params->int_mask & 0xFF, ®->imsk); if (ppi->ppi_control & PORT_DIR) { u32 hsync_width, vsync_width, vsync_period; @@ -288,10 +287,10 @@ static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params) * params->bpp / params->dlen; vsync_width = params->vsync * samples_per_line; vsync_period = samples_per_line * params->frame; - bfin_write32(®->fs1_wlhb, hsync_width); - bfin_write32(®->fs1_paspl, samples_per_line); - bfin_write32(®->fs2_wlvb, vsync_width); - bfin_write32(®->fs2_palpf, vsync_period); + writel(hsync_width, ®->fs1_wlhb); + writel(samples_per_line, ®->fs1_paspl); + writel(vsync_width, ®->fs2_wlvb); + writel(vsync_period, ®->fs2_palpf); } break; } @@ -313,7 +312,6 @@ static int ppi_set_params(struct ppi_if *ppi, struct ppi_params *params) set_dma_y_count(info->dma_ch, params->height); set_dma_config(info->dma_ch, dma_config); - SSYNC(); return 0; } -- 1.7.9.5