From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761523AbbA3L2I (ORCPT ); Fri, 30 Jan 2015 06:28:08 -0500 Received: from regular1.263xmail.com ([211.150.99.137]:59889 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751533AbbA3L2F (ORCPT ); Fri, 30 Jan 2015 06:28:05 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: ykk@rock-chips.com X-FST-TO: airlied@linux.ie X-SENDER-IP: 121.15.173.1 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <30072d34e135f5d32893c651e8ac2ab5> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Yakir Yang To: David Airlie , Russell King , Philipp Zabel Cc: Fabio Estevam , Shawn Guo , Rob Clark , Mark Yao , Daniel Vetter , Yakir Yang , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, djkurtz@chromium.org, dbehr@chromoum.org, mmind00@googlemail.com, dianders@chromium.org, marcheu@chromium.org, rockchip-discuss@chromium.org Subject: [PATCH v2 02/12] drm: bridge/dw_hdmi: add audio sample channel status setting Date: Fri, 30 Jan 2015 06:27:10 -0500 Message-Id: <1422617230-25303-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1422617031-25098-1-git-send-email-ykk@rock-chips.com> References: <1422617031-25098-1-git-send-email-ykk@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When transmitting IEC60985 linear PCM audio, we configure the Aduio Sample Channel Status information of all the channel status bits in the IEC60958 frame. Signed-off-by: Yakir Yang --- Changes in v2: - Add audio sample channel status setting drivers/gpu/drm/bridge/dw_hdmi.c | 41 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/bridge/dw_hdmi.h | 20 ++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index 423addc..2ded957 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -204,6 +204,47 @@ static void hdmi_regenerate_n_cts(struct dw_hdmi *hdmi, unsigned int n, hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); } +static void hdmi_set_schnl(struct dw_hdmi *hdmi) +{ + u8 aud_schnl_samplerate; + + switch (hdmi->sample_rate) { + case 32000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K; + break; + case 44100: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1; + break; + case 48000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K; + break; + case 88200: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2; + break; + case 96000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K; + break; + case 176400: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4; + break; + case 192000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K; + break; + case 768000: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K; + break; + default: + aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1; + break; + } + + /* set channel status register */ + hdmi_modb(hdmi, aud_schnl_samplerate, + HDMI_FC_AUDSCHNLS7_SMPRATE_MASK, HDMI_FC_AUDSCHNLS7); + hdmi_writeb(hdmi, ((~aud_schnl_samplerate) << 4) | 0x2, + HDMI_FC_AUDSCHNLS8); +} + static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk, unsigned int ratio) { diff --git a/drivers/gpu/drm/bridge/dw_hdmi.h b/drivers/gpu/drm/bridge/dw_hdmi.h index bc53452..603e645 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.h +++ b/drivers/gpu/drm/bridge/dw_hdmi.h @@ -162,6 +162,17 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 +#define HDMI_FC_AUDSV 0x1065 +#define HDMI_FC_AUDSU 0x1066 +#define HDMI_FC_AUDSCHNLS0 0x1067 +#define HDMI_FC_AUDSCHNLS1 0x1068 +#define HDMI_FC_AUDSCHNLS2 0x1069 +#define HDMI_FC_AUDSCHNLS3 0x106a +#define HDMI_FC_AUDSCHNLS4 0x106b +#define HDMI_FC_AUDSCHNLS5 0x106c +#define HDMI_FC_AUDSCHNLS6 0x106d +#define HDMI_FC_AUDSCHNLS7 0x106e +#define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 #define HDMI_FC_DATACH1FILL 0x1071 #define HDMI_FC_DATACH2FILL 0x1072 @@ -731,6 +742,15 @@ enum { /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, + HDMI_FC_AUDSCHNLS7_SMPRATE_MASK = 0x0f, + HDMI_FC_AUDSCHNLS7_SMPRATE_192K = 0xe, + HDMI_FC_AUDSCHNLS7_SMPRATE_176K4 = 0xc, + HDMI_FC_AUDSCHNLS7_SMPRATE_96K = 0xa, + HDMI_FC_AUDSCHNLS7_SMPRATE_768K = 0x9, + HDMI_FC_AUDSCHNLS7_SMPRATE_88K2 = 0x8, + HDMI_FC_AUDSCHNLS7_SMPRATE_32K = 0x3, + HDMI_FC_AUDSCHNLS7_SMPRATE_48K = 0x2, + HDMI_FC_AUDSCHNLS7_SMPRATE_44K1 = 0x0, /* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, -- 2.1.2