From: Scott Wood <scottwood@freescale.com>
To: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
<linux-kernel@vger.kernel.org>, <linuxppc-dev@lists.ozlabs.org>,
"Joakim Tjernlund" <joakim.tjernlund@transmode.se>
Subject: Re: [PATCH v3 00/11] powerpc8xx: Further optimisation of TLB handling
Date: Tue, 3 Feb 2015 11:17:37 -0600 [thread overview]
Message-ID: <1422983857.12631.2.camel@aoeu.buserror.net> (raw)
In-Reply-To: <20150203113816.B4B991A5F12@localhost.localdomain>
On Tue, 2015-02-03 at 12:38 +0100, Christophe Leroy wrote:
> This patchset provides a further optimisation of TLB handling in the 8xx.
> Main changes are based on:
> - Using processor handling of PGD/PTE Validity bits instead of testing ourselves
> the entries validity
> - Aligning PGD address to allow direct bit manipulation
> - Not saving registers like CR when not needed
>
> It also adds support to any TASK_SIZE
Please respin with just the changes that haven't already been applied to
my next branch.
-Scott
prev parent reply other threads:[~2015-02-03 17:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-03 11:38 Christophe Leroy
2015-02-03 17:17 ` Scott Wood [this message]
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