From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757984AbbBEQZK (ORCPT ); Thu, 5 Feb 2015 11:25:10 -0500 Received: from mga09.intel.com ([134.134.136.24]:32029 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753916AbbBEQZI (ORCPT ); Thu, 5 Feb 2015 11:25:08 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="450294303" Message-ID: <1423153467.22217.16.camel@theros.lm.intel.com> Subject: Re: [PATCH v3 0/2] add support for new persistent memory instructions From: Ross Zwisler To: linux-kernel@vger.kernel.org Cc: H Peter Anvin , Ingo Molnar , Thomas Gleixner , Borislav Petkov Date: Thu, 05 Feb 2015 09:24:27 -0700 In-Reply-To: <1422377631-8986-1-git-send-email-ross.zwisler@linux.intel.com> References: <1422377631-8986-1-git-send-email-ross.zwisler@linux.intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4 (3.10.4-4.fc20.rez) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2015-01-27 at 09:53 -0700, Ross Zwisler wrote: > This patch set adds support for two new persistent memory instructions, pcommit > and clwb. These instructions were announced in the document "Intel > Architecture Instruction Set Extensions Programming Reference" with reference > number 319433-022. > > https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf > > These patches apply cleanly to v3.19-rc6. > > Changes from v2: > > - Added instruction descriptions and flows to the patch descriptions. > - Added needed sfence to pcommit alternatives assembly. The inline function > is now called pcommit_sfence(). If pcommit is not supported on the platform > both the pcommit and the sfence will be nops. > > Cc: H Peter Anvin > Cc: Ingo Molnar > Cc: Thomas Gleixner > Cc: Borislav Petkov > > Ross Zwisler (2): > x86: Add support for the pcommit instruction > x86: Add support for the clwb instruction > > arch/x86/include/asm/cpufeature.h | 2 ++ > arch/x86/include/asm/special_insns.h | 22 ++++++++++++++++++++++ > 2 files changed, 24 insertions(+) Ping? :)