From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933144AbbBJOVq (ORCPT ); Tue, 10 Feb 2015 09:21:46 -0500 Received: from regular1.263xmail.com ([211.150.99.131]:56161 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932770AbbBJOVo (ORCPT ); Tue, 10 Feb 2015 09:21:44 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: ykk@rock-chips.com X-FST-TO: airlied@linux.ie X-SENDER-IP: 218.211.38.238 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Yakir Yang To: David Airlie , Russell King , Philipp Zabel Cc: Fabio Estevam , Shawn Guo , Rob Clark , Mark Yao , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Sean Cross , Jyri Sarha , Ben Zhang , alsa-devel@alsa-project.org, Heiko Stuebner , linux-arm-kernel@lists.infradead.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org, djkurtz@chromium.org, mmind00@googlemail.com, dianders@chromium.org, marcheu@chromium.org, linux-rockchip@lists.infradead.org, Yakir Yang Subject: [RFC PATCH 0/1] Improve eye-diagram & single-ended test for rk3288 hdmi Date: Tue, 10 Feb 2015 22:20:51 +0800 Message-Id: <1423578051-19425-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1423577791-19238-1-git-send-email-ykk@rock-chips.com> References: <1423577791-19238-1-git-send-email-ykk@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RK3288 hdmi eye-diagram test would fail when pixel clock is 148.5MHz, and single-ended test would failed when display mode is 74.25MHz. - Fix some code style, leave space for next patches. - For hdmi eye-diagram test, we turn on the Transmitter Trailer-B and improve slopeboost to 25%-30% decrease. - For hdmi single-ended test, we set CKLVL & TXLVL to 17 when pixel clock is 74.25MHz, keep CKLVL & TXLVL to 13 when pixel clock is 148.5MHz. Yakir Yang (1): drm: bridge/dw_hdmi: fixed codec style drivers/gpu/drm/bridge/dw_hdmi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.7.9.5