[PATCH 2/2] perf/x86: Provide TSC for PERF_SAMPLE_CLOCK_ARCH

[Adrian Hunter <adrian.hunter@intel.com>]

Provide TSC for PERF_SAMPLE_CLOCK_ARCH. This is needed
to match perf events against hardware traces like
Intel PT.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
 arch/x86/include/asm/perf_event.h |  6 ++++++
 arch/x86/kernel/cpu/perf_event.c  | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index dc0f6ed..ced9b5f 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -261,6 +261,12 @@ struct perf_guest_switch_msr {
 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
 extern void perf_check_microcode(void);
+
+#ifdef CONFIG_X86_TSC
+#define HAVE_PERF_SAMPLE_CLOCK_ARCH 1
+u64 perf_sample_clock_arch(void);
+#endif
+
 #else
 static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
 {
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 8271d6b..23ae9d4 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -2256,3 +2256,13 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
 	cap->events_mask_len	= x86_pmu.events_mask_len;
 }
 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
+
+#ifdef CONFIG_X86_TSC
+u64 perf_sample_clock_arch(void)
+{
+	u64 tsc;
+
+	rdtscll(tsc);
+	return tsc;
+}
+#endif
-- 
1.9.1