From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755084AbbB0Rsr (ORCPT ); Fri, 27 Feb 2015 12:48:47 -0500 Received: from mga03.intel.com ([134.134.136.65]:33082 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754742AbbB0Rsk (ORCPT ); Fri, 27 Feb 2015 12:48:40 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,661,1418112000"; d="scan'208";a="533827086" From: Andi Kleen To: peterz@infradead.org Cc: linux-kernel@vger.kernel.org, eranian@google.com, Andi Kleen Subject: [PATCH 1/3] perf, x86: Reset more state in PMU reset Date: Fri, 27 Feb 2015 09:48:30 -0800 Message-Id: <1425059312-18217-2-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1425059312-18217-1-git-send-email-andi@firstfloor.org> References: <1425059312-18217-1-git-send-email-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen The PMU reset code didn't quite keep up with newer PMU features. Improve it a bit to really reset a modern PMU: - Clear all overflow status - Clear LBRs and freezing state - Disable fixed counters too Signed-off-by: Andi Kleen --- arch/x86/kernel/cpu/perf_event_intel.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 3c024ba..0a48094 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1596,6 +1596,17 @@ static void intel_pmu_reset(void) if (ds) ds->bts_index = ds->bts_buffer_base; + /* Ack all overflows and disable fixed counters */ + if (x86_pmu.version >= 2) { + intel_pmu_ack_status(intel_pmu_get_status()); + wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); + } + + /* Reset LBRs and LBR freezing */ + if (x86_pmu.lbr_nr) + update_debugctlmsr(get_debugctlmsr() & + ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR)); + local_irq_restore(flags); } -- 1.9.3