From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751649AbbCKMIg (ORCPT ); Wed, 11 Mar 2015 08:08:36 -0400 Received: from mail-db3on0117.outbound.protection.outlook.com ([157.55.234.117]:51072 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750960AbbCKMIe (ORCPT ); Wed, 11 Mar 2015 08:08:34 -0400 From: Gaetan Hug To: CC: , , , , Gaetan Hug Subject: [PATCH RESEND] pwm: mxs: fix period divider computation Date: Wed, 11 Mar 2015 13:08:12 +0100 Message-ID: <1426075692-19340-1-git-send-email-ghug@induct.be> X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [91.183.127.4] X-ClientProxiedBy: DBXPR04CA0025.eurprd04.prod.outlook.com (10.141.8.153) To HE1PR01MB0811.eurprd01.prod.exchangelabs.com (25.162.22.153) Authentication-Results: gmail.com; dkim=none (message not signed) header.d=none; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:HE1PR01MB0811; X-Forefront-Antispam-Report: BMV:1;SFV:NSPM;SFS:(10019020)(6009001)(47776003)(42186005)(48376002)(86362001)(40100003)(74482002)(46102003)(2351001)(50986999)(87976001)(110136001)(77156002)(66066001)(33646002)(53416004)(36756003)(50466002)(62966003)(92566002)(122386002)(19580395003)(19580405001)(7059030);DIR:OUT;SFP:1102;SCL:1;SRVR:HE1PR01MB0811;H:ind-lt-007.induct.loc;FPR:;SPF:None;MLV:sfv;LANG:en; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5002009)(5005006);SRVR:HE1PR01MB0811;BCL:0;PCL:0;RULEID:;SRVR:HE1PR01MB0811; X-Forefront-PRVS: 0512CC5201 X-OriginatorOrg: induct.be X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2015 12:08:29.7842 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR01MB0811 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver computes which clock divider it sould be using from the requested period. This computation assumes that the link between the register value and the actual divider value is raising 2 to the power of the registry value. div = 1 << regvalue This is true only for the first 5 values out of 8. Next values are 64, 256 and, 1024 - instead of 32, 64, 128. This affects only the users requesting a period > 0.04369s. Replace the computation with a look-up table. Signed-off-by: Gaetan Hug Acked-by: Shawn Guo --- drivers/pwm/pwm-mxs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c index f75ecb0..c65e183 100644 --- a/drivers/pwm/pwm-mxs.c +++ b/drivers/pwm/pwm-mxs.c @@ -35,6 +35,8 @@ #define PERIOD_CDIV(div) (((div) & 0x7) << 20) #define PERIOD_CDIV_MAX 8 +static unsigned const int cdiv[PERIOD_CDIV_MAX] = {1, 2, 4, 8, 16, 64, 256, 1024}; + struct mxs_pwm_chip { struct pwm_chip chip; struct clk *clk; @@ -54,13 +56,13 @@ static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, rate = clk_get_rate(mxs->clk); while (1) { - c = rate / (1 << div); + c = rate / cdiv[div]; c = c * period_ns; do_div(c, 1000000000); if (c < PERIOD_PERIOD_MAX) break; div++; - if (div > PERIOD_CDIV_MAX) + if (div >= PERIOD_CDIV_MAX) return -EINVAL; } -- 1.7.10.4