From: <jesse.larrew@amd.com>
To: <x86@kernel.org>
Cc: Joel Schopp <joel.schopp@amd.com>,
Tony Luck <tony.luck@intel.com>, Borislav Petkov <bp@alien8.de>,
Thomas Gleixner <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>, <linux-edac@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Jesse Larrew <jesse.larrew@amd.com>
Subject: [PATCH] mce: use safe MSR accesses
Date: Wed, 11 Mar 2015 17:09:38 -0500 [thread overview]
Message-ID: <1426111778-17942-1-git-send-email-jesse.larrew@amd.com> (raw)
From: Jesse Larrew <jesse.larrew@amd.com>
When running as a guest under kvm, it's possible that the MSR
being accessed may not be implemented. All MSR accesses should
be prepared to handle exceptions.
Signed-off-by: Jesse Larrew <jesse.larrew@amd.com>
---
arch/x86/kernel/cpu/mcheck/mce.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 61a9668ce..4151ba9 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1556,12 +1556,12 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
for (i = 0; i < ARRAY_SIZE(msrs); i++) {
- rdmsrl(msrs[i], val);
+ rdmsrl_safe(msrs[i], &val);
/* CntP bit set? */
if (val & BIT_64(62)) {
val &= ~BIT_64(62);
- wrmsrl(msrs[i], val);
+ wrmsrl_safe(msrs[i], val);
}
}
--
1.9.1
next reply other threads:[~2015-03-11 22:52 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-11 22:09 jesse.larrew [this message]
2015-03-11 22:47 ` Luck, Tony
2015-03-12 17:20 ` Joel Schopp
2015-03-12 17:30 ` Borislav Petkov
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