From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932244AbbCLNiA (ORCPT ); Thu, 12 Mar 2015 09:38:00 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:24680 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754839AbbCLNhs (ORCPT ); Thu, 12 Mar 2015 09:37:48 -0400 X-AuditID: cbfec7f5-b7fc86d0000066b7-72-550196130cd3 From: Andrzej Hajda To: Kukjin Kim Cc: Andrzej Hajda , Marek Szyprowski , Kyungmin Park , javier.martinez@collabora.co.uk, Liquid.Acid@gmx.net, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 RESEND 3/4] ARM: dts: exynos5420: add async-bridge clocks to disp1 power domain Date: Thu, 12 Mar 2015 14:37:10 +0100 Message-id: <1426167431-24470-4-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1426167431-24470-1-git-send-email-a.hajda@samsung.com> References: <1426167431-24470-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprELMWRmVeSWpSXmKPExsVy+t/xK7rC0xhDDSbeMrK4te4cq8X8I0Di ytf3bBZHfxdY9D9+zWxxtukNu8Wmx9dYLS7vmsNmMeP8PiaLrp8/2SzWHrnL7sDt8ff5dRaP xZv2s3lsWtXJ5nG/+ziTx+Yl9R59W1YxenzeJBfAHsVlk5Kak1mWWqRvl8CVMWV3L2PBCs6K D58nMjUw3mXvYuTkkBAwkfgzZR8zhC0mceHeerYuRi4OIYGljBL/2h+yQzh9TBL7TlxgAqli E9CU+Lv5JlAVB4eIgKLE5gUKIDXMAo+ZJO5OXM0CUiMskCJxeFYbWD2LgKrE8nvLWEFsXgFn iVtdU5kgtslJnDw2GSzOKeAicf35JzYQWwio5mrvCdYJjLwLGBlWMYqmliYXFCel5xrpFSfm Fpfmpesl5+duYoSE49cdjEuPWR1iFOBgVOLhjehjCBViTSwrrsw9xCjBwawkwlvazhgqxJuS WFmVWpQfX1Sak1p8iJGJg1OqgdFGLaHp6tmCFCM7c6W9D/0EbQ4HvXsx6fpO7rVK7WJxmsZb p6W+mLaS4ZDciWqXk7dEA5/lmKq+FLltdf++yeGvK4yLyzKdrcNOaX22Py19jeEQa3m7/vtZ oisbT5fOODmLQ8LnL/+S7PurChSi1d5unOSXJWVvKrU1lmnuk6y1LctN9MwXZCmxFGckGmox FxUnAgACPO//JQIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER), therefore their clocks should be enabled during power domain switch. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Reviewed-by: Sylwester Nawrocki --- arch/arm/boot/dts/exynos5420.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c0e98cf..55e3887 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -283,9 +283,11 @@ <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, <&clock CLK_MOUT_SW_ACLK400>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>; + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_FIMD1>, <&clock CLK_MIXER>; clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2"; + "pclk1", "clk1", "pclk2", "clk2", + "asb0", "asb1"; }; pinctrl_0: pinctrl@13400000 { -- 1.9.1