From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932294AbbCLNit (ORCPT ); Thu, 12 Mar 2015 09:38:49 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:27548 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754104AbbCLNht (ORCPT ); Thu, 12 Mar 2015 09:37:49 -0400 X-AuditID: cbfec7f5-b7fc86d0000066b7-76-550196158ebe From: Andrzej Hajda To: Kukjin Kim Cc: Andrzej Hajda , Marek Szyprowski , Kyungmin Park , javier.martinez@collabora.co.uk, Liquid.Acid@gmx.net, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 RESEND 4/4] ARM: dts: exynos5420: add async-bridge clocks to gsc power domain Date: Thu, 12 Mar 2015 14:37:11 +0100 Message-id: <1426167431-24470-5-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1426167431-24470-1-git-send-email-a.hajda@samsung.com> References: <1426167431-24470-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnluLIzCtJLcpLzFFi42I5/e/4FV3RaYyhBo83CljcWneO1WL+ESBx 5et7Noujvwss+h+/ZrY42/SG3WLT42usFpd3zWGzmHF+H5NF18+fbBZrj9xld+D2+Pv8OovH 4k372Tw2repk87jffZzJY/OSeo++LasYPT5vkgtgj+KySUnNySxLLdK3S+DK2Pn3HGPBf7aK nnffmBoYv7B2MXJySAiYSLze+4UdwhaTuHBvPRuILSSwlFFi4nRxCLuPSeL1YhkQm01AU+Lv 5ptANRwcIgKKEpsXKHQxcnEwCzxmkrg7cTULSI2wQJJEw89/YDUsAqoSs7qYQMK8As4Srw71 Qa2Skzh5bDLYCZwCLhLXn3+CWusscbX3BOsERt4FjAyrGEVTS5MLipPSc430ihNzi0vz0vWS 83M3MUIC8esOxqXHrA4xCnAwKvHwRvQxhAqxJpYVV+YeYpTgYFYS4S1tZwwV4k1JrKxKLcqP LyrNSS0+xMjEwSnVwNjZWlcZkCK1fsbVz9uXdmi7nrVRmJTTrNlStVG9fdejKA5eLs88qfaz B/YXlcsltH9mbMt5Odm15n3TO8lLaSsMyoI/r1MR/zRXXko2/MJBta6AOef9aiZLNh5WL7Tj lVf/OePi9b0xcbu2z7GbeX0BS0KD7so97p3hEe/SzHfJ9xz55i6aq8RSnJFoqMVcVJwIAPtF axkiAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Both GSCALER IPs in gsc power domain have async-bridges (to FIMD and MIXER), therefore their clocks should be enabled during power domain switch. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 55e3887..4eaeabe 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -251,6 +251,8 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; + clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "asb0", "asb1"; }; isp_pd: power-domain@10044020 { -- 1.9.1