From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965485AbbCPTCj (ORCPT ); Mon, 16 Mar 2015 15:02:39 -0400 Received: from mail-we0-f177.google.com ([74.125.82.177]:35398 "EHLO mail-we0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934367AbbCPTBu (ORCPT ); Mon, 16 Mar 2015 15:01:50 -0400 From: LABBE Corentin To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, maxime.ripard@free-electrons.com, linux@arm.linux.org.uk, herbert@gondor.apana.org.au, davem@davemloft.net, akpm@linux-foundation.org, gregkh@linuxfoundation.org, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, linux-sunxi@googlegroups.com, LABBE Corentin Subject: [PATCH v6 1/4] ARM: sun7i: dt: Add Security System to A20 SoC DTS Date: Mon, 16 Mar 2015 20:01:19 +0100 Message-Id: <1426532482-28830-2-git-send-email-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.0.5 In-Reply-To: <1426532482-28830-1-git-send-email-clabbe.montjoie@gmail.com> References: <1426532482-28830-1-git-send-email-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms. It could be found on many Allwinner SoC. This patch enable the Security System on the Allwinner A20 SoC Device-tree. Signed-off-by: LABBE Corentin --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 3a8530b..8995bec 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -680,6 +680,14 @@ status = "disabled"; }; + crypto: crypto-engine@01c15000 { + compatible = "allwinner,sun7i-a20-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <0 86 4>; + clocks = <&ahb_gates 5>, <&ss_clk>; + clock-names = "ahb", "mod"; + }; + spi2: spi@01c17000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c17000 0x1000>; -- 2.0.5