From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752957AbbCWMcO (ORCPT ); Mon, 23 Mar 2015 08:32:14 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:26385 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752200AbbCWMcL (ORCPT ); Mon, 23 Mar 2015 08:32:11 -0400 From: Markos Chandras To: CC: Markos Chandras , Daniel Lezcano , Thomas Gleixner , "Jason Cooper" , Andrew Bresticker , Qais Yousef , Subject: [PATCH 0/3] GIC counter fixes Date: Mon, 23 Mar 2015 12:32:00 +0000 Message-ID: <1427113923-9840-1-git-send-email-markos.chandras@imgtec.com> X-Mailer: git-send-email 2.3.3 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.154.138] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Here are a few patches to ensure the GIC counter is running before we attempt to use it since the default value on a MIPS core can be '1' which means the GIC counter will be stopped after a CPU reset. These patches are based on 4.0-rc1. Markos Chandras (3): irqchip: irq-mips-gic: Add new functions to start/stop the GIC counter clocksource: mips-gic-timer: Ensure GIC counter is running MIPS: Malta: malta-time: Ensure GIC counter is running arch/mips/mti-malta/malta-time.c | 4 +++- drivers/clocksource/mips-gic-timer.c | 3 +++ drivers/irqchip/irq-mips-gic.c | 21 +++++++++++++++++++++ include/linux/irqchip/mips-gic.h | 2 ++ 4 files changed, 29 insertions(+), 1 deletion(-) -- 2.3.3