From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752729AbbCXNbC (ORCPT ); Tue, 24 Mar 2015 09:31:02 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37033 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752646AbbCXNbA (ORCPT ); Tue, 24 Mar 2015 09:31:00 -0400 From: Stephane Viau To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com, Stephane Viau Subject: [PATCH] rnndb/mdp5: Add some CTL flush bits Date: Tue, 24 Mar 2015 09:30:50 -0400 Message-Id: <1427203850-4647-1-git-send-email-sviau@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1427203802-4104-2-git-send-email-sviau@codeaurora.org> References: <1427203802-4104-2-git-send-email-sviau@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau --- rnndb/mdp/mdp5.xml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml index 423249a..03dcc3a 100644 --- a/rnndb/mdp/mdp5.xml +++ b/rnndb/mdp/mdp5.xml @@ -250,11 +250,19 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> + + + + + + + + -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project