From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753529AbbC3S6F (ORCPT ); Mon, 30 Mar 2015 14:58:05 -0400 Received: from mga14.intel.com ([192.55.52.115]:53585 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752898AbbC3S5z (ORCPT ); Mon, 30 Mar 2015 14:57:55 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,495,1422950400"; d="scan'208";a="672743545" From: Andy Shevchenko To: Stephen Boyd , linux-kernel@vger.kernel.org, heikki.krogerus@linux.intel.com Cc: Andy Shevchenko Subject: [PATCH v2 1/2] clk: fractional-divider: switch to rational best approximation Date: Mon, 30 Mar 2015 21:57:48 +0300 Message-Id: <1427741869-239562-2-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1427741869-239562-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1427741869-239562-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch converts the code to use rational best approximation algorithm which is more precise. Suggested-by: Stephen Boyd Signed-off-by: Andy Shevchenko --- drivers/clk/Kconfig | 3 +-- drivers/clk/clk-fractional-divider.c | 39 ++++++++++++++---------------------- 2 files changed, 16 insertions(+), 26 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 0b474a0..46d90a9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -14,6 +14,7 @@ config COMMON_CLK select HAVE_CLK_PREPARE select CLKDEV_LOOKUP select SRCU + select RATIONAL ---help--- The common clock framework is a single definition of struct clk, useful across many platforms, as well as an @@ -63,7 +64,6 @@ config COMMON_CLK_SI5351 tristate "Clock driver for SiLabs 5351A/B/C" depends on I2C select REGMAP_I2C - select RATIONAL ---help--- This driver supports Silicon Labs 5351A/B/C programmable clock generators. @@ -139,7 +139,6 @@ config COMMON_CLK_CDCE706 tristate "Clock driver for TI CDCE706 clock synthesizer" depends on I2C select REGMAP_I2C - select RATIONAL ---help--- This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 6aa72d9..9c53704 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -7,13 +7,14 @@ * * Adjustable fractional divider clock implementation. * Output rate = (m / n) * parent_rate. + * Uses rational best approximation algorithm. */ #include #include #include #include -#include +#include #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) @@ -21,9 +22,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_fractional_divider *fd = to_clk_fd(hw); + unsigned long m, n; unsigned long flags = 0; - u32 val, m, n; - u64 ret; + u32 val; if (fd->lock) spin_lock_irqsave(fd->lock, flags); @@ -39,30 +40,22 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, if (!n || !m) return parent_rate; - ret = (u64)parent_rate * m; - do_div(ret, n); - - return ret; + return mult_frac(parent_rate, m, n); } static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) + unsigned long *parent_rate) { struct clk_fractional_divider *fd = to_clk_fd(hw); - unsigned maxn = (fd->nmask >> fd->nshift) + 1; - unsigned div; + unsigned long m, n; - if (!rate || rate >= *prate) - return *prate; + if (!rate || rate >= *parent_rate) + return *parent_rate; - div = gcd(*prate, rate); - - while ((*prate / div) > maxn) { - div <<= 1; - rate <<= 1; - } + rational_best_approximation(rate, *parent_rate, + fd->mmask >> fd->mshift, fd->nmask >> fd->nshift, &m, &n); - return rate; + return mult_frac(rate, m, n); } static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, @@ -70,13 +63,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_fractional_divider *fd = to_clk_fd(hw); unsigned long flags = 0; - unsigned long div; - unsigned n, m; + unsigned long n, m; u32 val; - div = gcd(parent_rate, rate); - m = rate / div; - n = parent_rate / div; + rational_best_approximation(rate, parent_rate, + fd->mmask >> fd->mshift, fd->nmask >> fd->nshift, &m, &n); if (fd->lock) spin_lock_irqsave(fd->lock, flags); -- 2.1.4