From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752975AbbDBPYR (ORCPT ); Thu, 2 Apr 2015 11:24:17 -0400 Received: from mga02.intel.com ([134.134.136.20]:22391 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752091AbbDBPYP (ORCPT ); Thu, 2 Apr 2015 11:24:15 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,511,1422950400"; d="scan'208";a="707971783" From: kan.liang@intel.com To: a.p.zijlstra@chello.nl Cc: ak@linux.intel.com, linux-kernel@vger.kernel.org, Kan Liang Subject: [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack Date: Thu, 2 Apr 2015 04:12:57 -0400 Message-Id: <1427962377-40955-1-git-send-email-kan.liang@intel.com> X-Mailer: git-send-email 1.8.3.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang Same as Haswell, Broadwell also support LBR callstack. Signed-off-by: Kan Liang --- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index fc6dbc4..4b61fe9 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2787,7 +2787,7 @@ __init int intel_pmu_init(void) hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM; - intel_pmu_lbr_init_snb(); + intel_pmu_lbr_init_hsw(); x86_pmu.event_constraints = intel_bdw_event_constraints; x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; -- 1.8.3.1