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From: Rhyland Klein <rklein@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Alexandre Courbot <gnurou@gmail.com>,
	Bill Huang <bilhuang@nvidia.com>,
	Paul Walmsley <pwalmsley@nvidia.com>,
	linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org, Rhyland Klein <rklein@nvidia.com>
Subject: [PATCH 05/19] clk: tegra: pll: update warning msg
Date: Fri, 24 Apr 2015 12:47:45 -0400	[thread overview]
Message-ID: <1429894079-25052-6-git-send-email-rklein@nvidia.com> (raw)
In-Reply-To: <1429894079-25052-1-git-send-email-rklein@nvidia.com>

Swap out the generic WARN_ON with a WARN which gives more
information about what is happening.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
---
 drivers/clk/tegra/clk-pll.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index d287df90cfc0..61763c765f4c 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -695,7 +695,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 
 	pdiv = _hw_to_p_div(hw, cfg.p);
 	if (pdiv < 0) {
-		WARN_ON(1);
+		WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
+			__clk_get_name(hw->clk), cfg.p);
 		pdiv = 1;
 	}
 
-- 
1.7.9.5


  parent reply	other threads:[~2015-04-24 16:48 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-24 16:47 [PATCH 00/19] Tegra210 Clock Support Rhyland Klein
2015-04-24 16:47 ` [PATCH 01/19] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-04-24 16:47 ` [PATCH 02/19] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-04-24 16:47 ` [PATCH 03/19] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-04-24 16:47 ` [PATCH 04/19] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-04-24 16:47 ` Rhyland Klein [this message]
2015-04-24 16:47 ` [PATCH 06/19] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-04-24 16:47 ` [PATCH 07/19] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-04-24 16:47 ` [PATCH 08/19] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-04-24 16:47 ` [PATCH 09/19] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-04-24 16:47 ` [PATCH 10/19] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-04-24 16:47 ` [PATCH 11/19] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-04-24 16:47 ` [PATCH 12/19] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-04-24 16:47 ` [PATCH 13/19] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-04-27 14:10   ` Peter De Schrijver
2015-04-24 16:47 ` [PATCH 14/19] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-04-24 16:47 ` [PATCH 15/19] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-04-24 16:47 ` [PATCH 16/19] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-04-27 14:19   ` Peter De Schrijver
2015-04-27 14:30   ` Peter De Schrijver
2015-04-24 16:47 ` [PATCH 17/19] clk: tegra: pll: Fix _pll_ramp_calc_pll logic Rhyland Klein
2015-04-24 16:47 ` [PATCH 18/19] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-04-24 16:47 ` [PATCH 19/19] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-04-27 14:47   ` Peter De Schrijver

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