From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752051AbbEGPRh (ORCPT ); Thu, 7 May 2015 11:17:37 -0400 Received: from mail-bl2on0063.outbound.protection.outlook.com ([65.55.169.63]:32001 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752006AbbEGPRc (ORCPT ); Thu, 7 May 2015 11:17:32 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; codeaurora.org; dkim=none (message not signed) header.d=none; Authentication-Results: codeaurora.org; dkim=none (message not signed) header.d=none; From: To: , CC: , , , , , , , , "Dinh Nguyen" Subject: [PATCHv3 0/4] clk: socfpga: Add clock driver for Arria10 Date: Thu, 7 May 2015 10:11:59 -0500 Message-ID: <1431011523-10049-1-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.2.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BN1PR02CA0026.namprd02.prod.outlook.com (10.141.56.26) To BN3PR03MB1366.namprd03.prod.outlook.com (25.163.34.152) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1366;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR0301MB0835; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:;UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BN3PR03MB1366;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1366;BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BN3PR0301MB0835;BCL:0;PCL:0;RULEID:;SRVR:BN3PR0301MB0835; X-Forefront-PRVS: 056929CBB8 X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(6009001)(50986999)(48376002)(229853001)(33646002)(189998001)(19580405001)(19580395003)(50226001)(50466002)(42186005)(53416004)(77096005)(47776003)(40100003)(66066001)(62966003)(77156002)(92566002)(122386002)(5001770100001)(5001960100002)(86362001)(5001920100001)(86152002)(107886002)(87976001)(46102003)(4001430100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR03MB1366;H:linux-builds1.altera.com;FPR:;SPF:None;MLV:sfv;LANG:en; X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1366 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: BY2FFO11FD044.protection.gbl X-Forefront-Antispam-Report: CIP:66.35.236.227;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(339900001)(189002)(199003)(105606002)(122386002)(33646002)(189998001)(92566002)(5001960100002)(66066001)(81156007)(107886002)(5001770100001)(48376002)(46102003)(19580405001)(50466002)(40100003)(77156002)(62966003)(50226001)(86362001)(47776003)(229853001)(16796002)(77096005)(86152002)(50986999)(53416004)(87936001)(19580395003)(85426001)(6806004)(106466001)(7099028)(4001430100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR0301MB0835;H:sj-itexedge03.altera.priv.altera.com;FPR:;SPF:Fail;MLV:ovrnspm;MX:1;A:0;PTR:InfoDomainNonexistent;LANG:en; X-Forefront-PRVS: 056929CBB8 X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2015 15:17:28.2266 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a;Ip=[66.35.236.227];Helo=[sj-itexedge03.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR0301MB0835 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dinh Nguyen Hi, This patch series add the clock driver for the Arria10 platform. Although the Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the differences are enough to warrant it's own driver, rather than polluting the existing driver with platform lookups. v3: - Fix sparse warning of assigning an integer 0 instead of NULL to a pointer. v2: - Update the DTS bindings doucment to have the new Arria10 clocks. - Add an l4_sys_free_clk node. The l4_sys_free_clk is similar to the l4_sp_clk, but cannot be gated. *** BLURB HERE *** Dinh Nguyen (4): clk: socfpga: update clk.h so for Arria10 platform to use clk: socfpga: add a clock driver for the Arria 10 platform ARM: socfpga: dts: add clocks to the Arria10 platform Documentation: DT bindings: document the clocks for Arria10 .../devicetree/bindings/clock/altr_socfpga.txt | 17 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 309 ++++++++++++++++++++- drivers/clk/socfpga/Makefile | 1 + drivers/clk/socfpga/clk-gate-a10.c | 187 +++++++++++++ drivers/clk/socfpga/clk-gate.c | 4 - drivers/clk/socfpga/clk-periph-a10.c | 131 +++++++++ drivers/clk/socfpga/clk-pll-a10.c | 132 +++++++++ drivers/clk/socfpga/clk.c | 7 +- drivers/clk/socfpga/clk.h | 10 +- 9 files changed, 782 insertions(+), 16 deletions(-) create mode 100644 drivers/clk/socfpga/clk-gate-a10.c create mode 100644 drivers/clk/socfpga/clk-periph-a10.c create mode 100644 drivers/clk/socfpga/clk-pll-a10.c -- 2.2.1