From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753536AbbE0S5P (ORCPT ); Wed, 27 May 2015 14:57:15 -0400 Received: from mail-bn1on0144.outbound.protection.outlook.com ([157.56.110.144]:53808 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752238AbbE0Syu (ORCPT ); Wed, 27 May 2015 14:54:50 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NP0V78-08-76K-02 X-M-MSG: From: Aravind Gopalakrishnan To: , , CC: , Subject: [PATCH 4/6] edac, mce_amd_inj: Add capability to trigger apic interrupts Date: Wed, 27 May 2015 14:03:36 -0500 Message-ID: <1432753418-2985-5-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.4.0 In-Reply-To: <1432753418-2985-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1432753418-2985-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BL2FFO11OLC009;1:OWvoyx7kHSmzB2APx89aRC/acQIWQYvC1Jisx0Aw2JJZNP6RNVGHk93jC4kvzyiVJFLrFuyPae4ptZoepZAIDQ32cOzFGcabBCGmyav/qNE7FLk/1ByUxLZzzvzPYHK1ODdB0aCbG7lZyJWCUK+vWCiytgiCJ5Uxa+nz9/3kW/DNX6gWbAJAL6P7E7cIuYE49+UMvQgkhAzcPXpTU5sDBtuqvxKR0N7GUvHKTOVMMG3zVet64NsI5zW/PX3lvq9aMCfmqyrVihClpUIZSgZhHQ== X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(199003)(189002)(106466001)(48376002)(62966003)(19580395003)(50226001)(53416004)(5001860100001)(64706001)(229853001)(47776003)(189998001)(46102003)(5001830100001)(50466002)(19580405001)(2201001)(92566002)(77156002)(87936001)(101416001)(86362001)(50986999)(5001770100001)(105586002)(36756003)(77096005)(2950100001)(4001540100001)(76176999)(68736005)(97736004);DIR:OUT;SFP:1102;SCL:1;SRVR:BLUPR02MB1107;H:atltwp02.amd.com;FPR:;SPF:None;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR02MB1107;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR02MB264; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(520003)(3002001);SRVR:BLUPR02MB1107;BCL:0;PCL:0;RULEID:;SRVR:BLUPR02MB1107; X-Forefront-PRVS: 05891FB07F X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2015 18:54:46.1355 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR02MB1107 X-OriginatorOrg: amd.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org With this extension to the flags attribute, deferred error interrupts and threshold interrupts can be triggered to test the apic interrupt handler functionality for these type of errors Signed-off-by: Aravind Gopalakrishnan --- drivers/edac/mce_amd_inj.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c index daec4af..f1c1433 100644 --- a/drivers/edac/mce_amd_inj.c +++ b/drivers/edac/mce_amd_inj.c @@ -34,12 +34,16 @@ static u8 n_banks; enum injection_type { SW_INJ = 0, /* SW injection, simply decode the error */ HW_INJ, /* Trigger a #MC */ + DFR_INT_INJ, /* Trigger Deferred error interrupt */ + THR_INT_INJ, /* Trigger threshold interrupt */ N_INJ_TYPES, }; static const char * const flags_options[] = { [SW_INJ] = "sw", [HW_INJ] = "hw", + [DFR_INT_INJ] = "dfr", + [THR_INT_INJ] = "thr", NULL }; @@ -191,6 +195,16 @@ static void trigger_mce(void *info) asm volatile("int $18"); } +static void trigger_dfr_int(void *info) +{ + asm volatile("int $244"); +} + +static void trigger_thr_int(void *info) +{ + asm volatile("int $249"); +} + static void do_inject(void) { u64 mcg_status = 0; @@ -202,6 +216,20 @@ static void do_inject(void) return; } + if (inj_type == DFR_INT_INJ) { + /* + * Ensure necessary status bits for deferred errors: + * a. MCx_STATUS[Deferred] is set - + * This is to ensure the error will be handled by the + * interrupt handler + * b. unset MCx_STATUS[UC] + * As deferred errors are _not_ UC + */ + + i_mce.status |= MCI_STATUS_DEFERRED; + i_mce.status |= (i_mce.status & ~MCI_STATUS_UC); + } + get_online_cpus(); if (!cpu_online(cpu)) goto err; @@ -228,7 +256,12 @@ static void do_inject(void) toggle_hw_mce_inject(cpu, false); - smp_call_function_single(cpu, trigger_mce, NULL, 0); + if (inj_type == DFR_INT_INJ) + smp_call_function_single(cpu, trigger_dfr_int, NULL, 0); + else if (inj_type == THR_INT_INJ) + smp_call_function_single(cpu, trigger_thr_int, NULL, 0); + else + smp_call_function_single(cpu, trigger_mce, NULL, 0); err: put_online_cpus(); -- 2.4.0