From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753248AbbE0SzC (ORCPT ); Wed, 27 May 2015 14:55:02 -0400 Received: from mail-bl2on0134.outbound.protection.outlook.com ([65.55.169.134]:9760 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752321AbbE0Syu (ORCPT ); Wed, 27 May 2015 14:54:50 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NP0V7A-07-OXV-02 X-M-MSG: From: Aravind Gopalakrishnan To: , , CC: , Subject: [PATCH 5/6] edac, mce_amd_inj: Add README file Date: Wed, 27 May 2015 14:03:37 -0500 Message-ID: <1432753418-2985-6-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.4.0 In-Reply-To: <1432753418-2985-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1432753418-2985-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1AFFO11FD027;1:I+6pXUK3tNeyopj2VXp3G7p/2MbJ6oxex3H6Mufj8yPRULod+VbfiGzdaJlUClg92Mwnj/qnanMgUjBaZiEf0hjpXLBSOjDFhmVdFN6npGqPR2u0ya6bgrxN/Qh6Vbb57lUW3kK9Lb3pKVL4R7fWLiOlQcGU/0baUl/2YfHI7q/NjQxJ/LumjZPmuM51RtPrHmz4rhyDZCO8VguL05QeWzmrVyu1fJGJo+3UdzAavxWwZpfX1VwrlXQAXRyMAqgQd0VksY057i4XkTBPYzt8gA== X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(199003)(189002)(53416004)(229853001)(5001860100001)(5001830100001)(19580395003)(5001770100001)(19580405001)(97736004)(4001540100001)(62966003)(76176999)(189998001)(77156002)(101416001)(2950100001)(106466001)(64706001)(36756003)(47776003)(46102003)(50986999)(77096005)(50466002)(105586002)(50226001)(2201001)(87936001)(86362001)(92566002)(68736005)(48376002);DIR:OUT;SFP:1102;SCL:1;SRVR:CY1PR02MB1117;H:atltwp01.amd.com;FPR:;SPF:None;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR02MB1117; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(520003)(5005006)(3002001);SRVR:CY1PR02MB1117;BCL:0;PCL:0;RULEID:;SRVR:CY1PR02MB1117; X-Forefront-PRVS: 05891FB07F X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2015 18:54:46.4975 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR02MB1117 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Provides information about each file and the usages. Signed-off-by: Aravind Gopalakrishnan --- drivers/edac/mce_amd_inj.c | 68 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 61 insertions(+), 7 deletions(-) diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c index f1c1433..ca5b29f 100644 --- a/drivers/edac/mce_amd_inj.c +++ b/drivers/edac/mce_amd_inj.c @@ -291,17 +291,71 @@ MCE_INJECT_GET(bank); DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n"); +static const char readme_msg[] = + "\nDescription of the files and their usages:\n\n" + "status: Set a value to be programmed into MCx_STATUS(bank)\n" + "\t The status bits provide insight into the type of\n" + "\t error that caused the MCE.\n\n" + "misc: Set value of MCx_MISC(bank)\n" + "\t misc register provides auxiliary info about the error. This\n" + "\t register is typically used for error thresholding purpose and\n" + "\t validity of the register is indicated by MCx_STATUS[MiscV]\n\n" + "addr: Error address value to be written to MCx_ADDR(bank)\n" + "\t This register is used to log address information associated\n" + "\t with the error.\n\n" + "Note: See respective BKDGs for the exact bit definitions of the\n" + "\t above registers as they mirror the MCi_[STATUS | MISC | ADDR]\n" + "\t hardware registers.\n\n" + "bank: Specify the bank you want to inject the error into.\n" + "\t The number of banks in a processor varies and is family/model\n" + "\t dependent. So, a sanity check performed while writing.\n" + "\t Writing to this file will trigger a #MC or APIC interrupts or\n" + "\t invoke the error decoder routines for AMD processors. The value\n" + "\t in 'flags' file decides which of above actions is triggered.\n\n" + "flags: Write to this file to speficy the error injection policy.\n" + "\t Allowed values:\n" + "\t\t\"sw\" - SW error injection, Only calls error decoder\n" + "\t\t\troutines to print error info in human readable format\n" + "\t\t\"hw\" - HW error injection, Forces a #MC,\n" + "\t\t\tcauses exception handler to handle the error\n" + "\t\t\tif UC or poll handler catches it if CE\n" + "\t\t\tWarning: Might cause system panic if MCx_STATUS[PCC]\n" + "\t\t\tis set. For debug purposes, consider setting\n" + "\t\t\t//mce/fake_panic\n" + "\t\t\"dfr\" - Trigger APIC interrupt for Deferred error\n" + "\t\t\tError is handled by deferred error apic handler if\n" + "\t\t\tfeature is present in HW.\n" + "\t\t\"thr\" - Trigger APIC interrupt for threshold error\n" + "\t\t\tError is handled by threshold apic handler\n\n" + "cpu: The cpu to inject the error on.\n\n" +; + +static ssize_t +inj_readme_read(struct file *filp, char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + return simple_read_from_buffer(ubuf, cnt, ppos, + readme_msg, strlen(readme_msg)); +} + +static const struct file_operations readme_fops = { + .read = inj_readme_read, +}; + static struct dfs_node { char *name; struct dentry *d; const struct file_operations *fops; + umode_t perm; } dfs_fls[] = { - { .name = "status", .fops = &status_fops }, - { .name = "misc", .fops = &misc_fops }, - { .name = "addr", .fops = &addr_fops }, - { .name = "bank", .fops = &bank_fops }, - { .name = "flags", .fops = &flags_fops }, - { .name = "cpu", .fops = &extcpu_fops }, + { .name = "status", .fops = &status_fops, S_IRUSR | S_IWUSR }, + { .name = "misc", .fops = &misc_fops, S_IRUSR | S_IWUSR }, + { .name = "addr", .fops = &addr_fops, S_IRUSR | S_IWUSR }, + { .name = "bank", .fops = &bank_fops, S_IRUSR | S_IWUSR }, + { .name = "flags", .fops = &flags_fops, S_IRUSR | S_IWUSR }, + { .name = "cpu", .fops = &extcpu_fops, S_IRUSR | S_IWUSR }, + { .name = "README", .fops = &readme_fops, S_IRUSR | S_IRGRP | + S_IROTH }, }; static int __init init_mce_inject(void) @@ -318,7 +372,7 @@ static int __init init_mce_inject(void) for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) { dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name, - S_IRUSR | S_IWUSR, + dfs_fls[i].perm, dfs_inj, &i_mce, dfs_fls[i].fops); -- 2.4.0