From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753486AbbE0S4s (ORCPT ); Wed, 27 May 2015 14:56:48 -0400 Received: from mail-bl2on0109.outbound.protection.outlook.com ([65.55.169.109]:40626 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751939AbbE0Syx (ORCPT ); Wed, 27 May 2015 14:54:53 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NP0V7D-08-76W-02 X-M-MSG: From: Aravind Gopalakrishnan To: , , CC: , Subject: [PATCH 6/6] edac, mce_amd_inj: Inject errors on NBC for bank 4 errors Date: Wed, 27 May 2015 14:03:38 -0500 Message-ID: <1432753418-2985-7-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.4.0 In-Reply-To: <1432753418-2985-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1432753418-2985-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1BFFO11FD018;1:Q63a2pFB91hjvvrXSZpFAhxJ9bOk8QL0e+JnK+9vqTy4gCOAR5T+bwlsEm6rUoe6yFF7n+kv/boric2OnNfoYrMoyCvhEgL9DQofNYMvrUUEqx6k59xF+F4796K3axhlrQg9OBSwhBS6tfb+O3EUscV/NC/2qvXFjyH9gCWIP/wQdtD++o+T1e61VKBJbbB+Pn32rUVAWYPly+m4DjuQPMtXJSpy8PcUHBnEe4skVb/jAZ1ahm86L2uPsKNLsK7e1eYzkUn724EYN5EGHSOZ7A== X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(189002)(199003)(229853001)(2201001)(101416001)(50986999)(76176999)(64706001)(87936001)(92566002)(86362001)(48376002)(50466002)(5001860100001)(77096005)(5001920100001)(68736005)(5001830100001)(53416004)(5001770100001)(77156002)(106466001)(36756003)(50226001)(46102003)(47776003)(189998001)(19580395003)(19580405001)(62966003)(4001540100001)(105586002)(97736004)(2950100001)(21314002);DIR:OUT;SFP:1102;SCL:1;SRVR:BLUPR02MB1106;H:atltwp02.amd.com;FPR:;SPF:None;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR02MB1106; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(520003)(3002001);SRVR:BLUPR02MB1106;BCL:0;PCL:0;RULEID:;SRVR:BLUPR02MB1106; X-Forefront-PRVS: 05891FB07F X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2015 18:54:50.4512 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR02MB1106 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For bank 4 errors, MCE logging and reporting is done only on node base cores. Refer D18F3x44[NbMcaToMstCpuEn] field in Fam10h and later BKDGs. This patch ensures that we inject the error on the node base core for bank 4 errors. Otherwise, triggering #MC or apic interrupts on a non node base core would not have any effect on the system. (i.e), we would not see any relevant output on kernel logs for the error we just injected. Signed-off-by: Aravind Gopalakrishnan --- drivers/edac/mce_amd_inj.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c index ca5b29f..bd44ba4 100644 --- a/drivers/edac/mce_amd_inj.c +++ b/drivers/edac/mce_amd_inj.c @@ -17,9 +17,12 @@ #include #include #include +#include #include +#include #include "mce_amd.h" +#include "amd64_edac.h" /* * Collect all the MCi_XXX settings @@ -205,6 +208,65 @@ static void trigger_thr_int(void *info) asm volatile("int $249"); } +static u32 amd_get_num_nodes(void) +{ + u32 nodes = 1; + + if (cpu_has_topoext) { + u32 ecx; + + ecx = cpuid_ecx(0x8000001e); + nodes = ((ecx >> 8) & 7) + 1; + } else if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { + u64 value; + + rdmsrl(MSR_FAM10H_NODE_ID, value); + nodes = ((value >> 3) & 7) + 1; + } + + return nodes; +} + +static u32 amd_get_nbc_for_node(int node_id) +{ + struct cpuinfo_x86 *c = &boot_cpu_data; + u32 nodes, cores_per_node; + + nodes = amd_get_num_nodes(); + cores_per_node = c->x86_max_cores / nodes; + + return cores_per_node * node_id; +} + +static void toggle_nb_mca_mst_cpu(u16 nid) +{ + struct pci_dev *F3 = node_to_amd_nb(nid)->misc; + u32 val; + int err; + + if (!F3) + return; + + err = pci_read_config_dword(F3, NBCFG, &val); + if (err) { + pr_err("%s: Error reading F%dx%03x.\n", __func__, + PCI_FUNC(F3->devfn), + NBCFG); + return; + } + + if (!(val & BIT(27))) { + pr_err("%s: BIOS not setting D18F3x44[NbMcaToMstCpuEn]." + "Doing that here\n", __func__); + val |= BIT(27); + err = pci_write_config_dword(F3, NBCFG, val); + if (err) + pr_err("%s: Error writing F%dx%03x.\n", __func__, + PCI_FUNC(F3->devfn), + NBCFG); + } +} + static void do_inject(void) { u64 mcg_status = 0; @@ -240,6 +302,20 @@ static void do_inject(void) if (!(i_mce.status & MCI_STATUS_PCC)) mcg_status |= MCG_STATUS_RIPV; + /* + * For multi node cpus, logging and reporting of bank == 4 errors + * happen only on the node base core. Refer D18F3x44[NbMcaToMstCpuEn] + * for Fam10h and later BKDGs + */ + if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) { + /* + * BIOS sets D18F3x44[NbMcaToMstCpuEn] by default. + * But make sure of it here just in case.. + */ + toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu)); + cpu = amd_get_nbc_for_node(amd_get_nb_id(cpu)); + } + toggle_hw_mce_inject(cpu, true); wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS, -- 2.4.0