From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756623AbbE2QrC (ORCPT ); Fri, 29 May 2015 12:47:02 -0400 Received: from mga02.intel.com ([134.134.136.20]:43417 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756149AbbE2Qqx (ORCPT ); Fri, 29 May 2015 12:46:53 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,518,1427785200"; d="scan'208";a="578885582" From: Ashok Raj To: linux-kernel@vger.kernel.org Cc: Ashok Raj , linux-edac@vger.kernel.org, Borislav Petkov , Tony Luck Subject: [Patch V1 0/3] x86 Local Machine Check Exception (LMCE) Date: Fri, 29 May 2015 09:27:59 -0700 Message-Id: <1432916882-1304-1-git-send-email-ashok.raj@intel.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Historically machine checks on Intel X86 processors have been broadcast to all logical processors in the system. Upcoming CPUs will support an opt-in mechanism to request some machine checks delivered to a single logical processor experiencing the fault. For more details see Vol3, Chapter 15, Machine Check Architecture. Ashok Raj (3): x86, mce: Add LMCE definitions. x86, mce: Add infrastructure required to support LMCE x86, mce: Handling LMCE events Documentation/x86/x86_64/boot-options.txt | 3 ++ arch/x86/include/asm/mce.h | 10 ++++ arch/x86/include/uapi/asm/msr-index.h | 2 + arch/x86/kernel/cpu/mcheck/mce.c | 28 ++++++++++-- arch/x86/kernel/cpu/mcheck/mce_intel.c | 76 +++++++++++++++++++++++++++++++ 5 files changed, 116 insertions(+), 3 deletions(-) -- 1.9.1