From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964786AbbFJHXy (ORCPT ); Wed, 10 Jun 2015 03:23:54 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:48795 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753565AbbFJHXr (ORCPT ); Wed, 10 Jun 2015 03:23:47 -0400 From: Murali Karicheri To: , , CC: Murali Karicheri Subject: [PATCH v1] spi: davinci: change the lower limit of pre-scale divider to 1 Date: Wed, 10 Jun 2015 03:23:42 -0400 Message-ID: <1433921022-13151-1-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SPI hardware spec for Keystone specify a lower value of 0 for pre-scale divider which determine what max value of spi clock (spi-max-frequency) the device can support. This translates to a clock divider of 2. So fix the lower limit value used for the boundary check in davinci_spi_get_prescale() function to 1 so that a maximum of spi device clock rate / 2 is possible to be set for spi-max-frequency. Signed-off-by: Murali Karicheri Acked-by: Sekhar Nori --- - Re-send with updates to commit log and PATCH prefix - Applies to v4.1 drivers/spi/spi-davinci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 5e99106..987afeb 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -265,7 +265,7 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); - if (ret < 3 || ret > 256) + if (ret < 1 || ret > 256) return -EINVAL; return ret - 1; -- 1.9.1