From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932126AbbFKOmR (ORCPT ); Thu, 11 Jun 2015 10:42:17 -0400 Received: from mail-bl2on0125.outbound.protection.outlook.com ([65.55.169.125]:19258 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753028AbbFKOmN (ORCPT ); Thu, 11 Jun 2015 10:42:13 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; amacapital.net; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NPSBI4-07-ZJY-02 X-M-MSG: From: Huang Rui To: Borislav Petkov , Andy Lutomirski , Thomas Gleixner , Peter Zijlstra , Ingo Molnar , "Rafael J. Wysocki" , "Len Brown" , John Stultz , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Weisbecker?= CC: , , Fengguang Wu , Aaron Lu , Suravee Suthikulanit , Tony Li , Huang Rui Subject: [PATCH v4 0/2] x86, mwaitt: introduce AMD mwaitt support Date: Thu, 11 Jun 2015 22:41:00 +0800 Message-ID: <1434033662-2291-1-git-send-email-ray.huang@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1BFFO11FD022;1:v97mQHdEluBO5hixyQfQ23pJvRyBVGoYTLoa2RFt7ybdUFngwf7bpnL6ijYXK0xpElHuIjA0EFHnx5YraCQ2i53dongqpvRw2gGqRPG42hRG8XE4UW53O3yT/iRcf4P8ytj9kH3jmt0cCG+EvAlXqCVCNyjcp6n+1pcBlg6H00bqjyVV5/VD7JpVlCiqhfBTzZeM2jj/E7NtTA+TxRDXxzEghVgGiMS7830NBKuiMvavFeYdb6tYqsDPQB9tgHLZHzklS/Q8u7Txok2r1pMwZBZlEJBGQguRcjpPT9EwPb+Yb06jdwsa3Iw5e/kHHP8Cy7aShwmX11cin3/9ruF2dPsYm4B6L08XcZAGBKOTztc= X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(209900001)(189002)(164054003)(199003)(15395725005)(105586002)(15975445007)(53416004)(77096005)(62966003)(77156002)(86362001)(50986999)(36756003)(50226001)(5003600100002)(92566002)(189998001)(5001770100001)(47776003)(48376002)(33646002)(50466002)(106466001)(101416001)(87936001)(229853001)(19580395003)(46102003)(6606295002);DIR:OUT;SFP:1102;SCL:1;SRVR:BN3PR02MB1109;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1109;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1256; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(520003)(3002001);SRVR:BN3PR02MB1109;BCL:0;PCL:0;RULEID:;SRVR:BN3PR02MB1109; X-Forefront-PRVS: 0604AFA86B X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2015 14:42:06.0004 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR02MB1109 X-OriginatorOrg: amd.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, This patch set introduces a new instruction support on AMD Carrizo (Family 15h, Model 60h-6fh). It adds mwaitx delay function with a configurable timer. Andy and Boris provide a suggestion which use mwaitx on delay method. Some discussions of the background, please see: http://marc.info/?l=linux-kernel&m=143202042530498&w=2 http://marc.info/?l=linux-kernel&m=143161327003541&w=2 http://marc.info/?l=linux-kernel&m=143222815331016&w=2 They are rebased on tip/master. Changes from v1 -> v2 - Remove mwaitx idle implementation since some disputes without power improvement. - Add a patch which implement another use case on delay. - Introduce a kernel parameter (delay) to make delay method configurable. Changes from v2 -> v3 - Add compared data on commit message - Remove kernel parameter - Add hint to avoid to access deep state in future - Update mwaitx delay method as Petter's suggestion Changes from v3 -> v4 - Put the description into comments I already do some testing with mwaitx on udelay. Test scenario: glb_loops = usec_to_tsc(delay_usec) rdtsc -> read TSC counters as start mwaitx_delay(glb_loops) rdtsc -> read TSC counters as end diff = end - start Compared the real TSC counts (diff), that means the loops of counter goes. And glb_loops is the input value of the EBX, that is the expect loops which user configures. Below is 10000 us of mwaitx delay, we could see about 1200 (diff - glb_loops) delayed with mwaitx. [ 2369.008651] start=4401974718758, end=4401992576888, diff=17858130, glb_loops=17856939 Thanks, Rui Huang Rui (2): x86, mwaitt: add monitorx and mwaitx instruction x86, mwaitt: introduce mwaix delay with a configurable timer arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/mwait.h | 51 +++++++++++++++++++++++++++++++++++++++ arch/x86/lib/delay.c | 41 ++++++++++++++++++++++++++++++- 3 files changed, 92 insertions(+), 1 deletion(-) -- 1.9.1