From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932338AbbFKOme (ORCPT ); Thu, 11 Jun 2015 10:42:34 -0400 Received: from mail-by2on0117.outbound.protection.outlook.com ([207.46.100.117]:33554 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752711AbbFKOmZ (ORCPT ); Thu, 11 Jun 2015 10:42:25 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; amacapital.net; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NPSBIG-08-AAJ-02 X-M-MSG: From: Huang Rui To: Borislav Petkov , Andy Lutomirski , Thomas Gleixner , Peter Zijlstra , Ingo Molnar , "Rafael J. Wysocki" , "Len Brown" , John Stultz , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Weisbecker?= CC: , , Fengguang Wu , Aaron Lu , Suravee Suthikulanit , Tony Li , Huang Rui Subject: [PATCH v4 2/2] x86, mwaitt: introduce mwaix delay with a configurable timer Date: Thu, 11 Jun 2015 22:41:02 +0800 Message-ID: <1434033662-2291-3-git-send-email-ray.huang@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434033662-2291-1-git-send-email-ray.huang@amd.com> References: <1434033662-2291-1-git-send-email-ray.huang@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1AFFO11FD037;1:jUlWE0M9AXCcr4qD41xAF4JAkuWzWjDA9PYsHS+MDtbobCZCc1rjr0EBwFjtoW1NZM1PetM+kjDaeyDPcS0W6/zixAuPZa2FOz2eHhUoAb2mkQvNcK7mnTBFLeLQvNbFM+6+pnuvhMa3rrufPMYxhfEfh9sd34jJ77rmINX0Q3762KURvShZsSPv16/6jUr08u3gbt4nJnzYcLc3oi1mKkvddh3WbuTbdVK7vBLK8fsl8IZCe1KbuQBi5ZCPf98IEuDkV+zKL3+lLAmyinOymUZzzke7qqifht107670qg9QxOZZBTkc/MNVkOU8EbkJVywiS+pCwJsm0cS10pP6v7/PTdiDwdZZQu2AF7BiQyI= X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(189002)(199003)(106466001)(76176999)(50986999)(50466002)(48376002)(50226001)(2950100001)(86362001)(101416001)(33646002)(87936001)(77096005)(5001770100001)(19580395003)(47776003)(62966003)(77156002)(19580405001)(46102003)(5003600100002)(36756003)(229853001)(189998001)(53416004)(92566002)(105586002);DIR:OUT;SFP:1102;SCL:1;SRVR:BY1PR02MB1116;H:atltwp02.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1116;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1225; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(520003)(3002001);SRVR:BY1PR02MB1116;BCL:0;PCL:0;RULEID:;SRVR:BY1PR02MB1116; X-Forefront-PRVS: 0604AFA86B X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2015 14:42:19.5701 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR02MB1116 X-OriginatorOrg: amd.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MWAITX can enable a timer and a corresponding timer value specified in SW P0 clocks. The SW P0 frequency is the same with TSC. The timer provides an upper bound on how long the instruction waits before exiting. The implementation of delay function in kernel can lerverage the timer of MWAITX. This patch provides a new method (delay_mwaitx) to measure delay time. Suggested-by: Andy Lutomirski Suggested-by: Borislav Petkov Suggested-by: Peter Zijlstra Signed-off-by: Huang Rui --- arch/x86/include/asm/mwait.h | 11 +++++++++++ arch/x86/lib/delay.c | 41 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h index 1fbc89d..9c8cccd 100644 --- a/arch/x86/include/asm/mwait.h +++ b/arch/x86/include/asm/mwait.h @@ -14,6 +14,8 @@ #define CPUID5_ECX_INTERRUPT_BREAK 0x2 #define MWAIT_ECX_INTERRUPT_BREAK 0x1 +#define MWAITX_ECX_TIMER_ENABLE BIT(1) +#define MWAITX_MAX_LOOPS ((u32)-1) static inline void __monitor(const void *eax, unsigned long ecx, unsigned long edx) @@ -104,4 +106,13 @@ static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) current_clr_polling(); } +static inline void mwaitx(unsigned long eax, unsigned long loops, + bool enable) +{ + if (enable) + __mwaitx(eax, loops, MWAITX_ECX_TIMER_ENABLE); + else + __mwaitx(eax, 0, 0); +} + #endif /* _ASM_X86_MWAIT_H */ diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c index 39d6a3d..9daf94a 100644 --- a/arch/x86/lib/delay.c +++ b/arch/x86/lib/delay.c @@ -20,6 +20,7 @@ #include #include #include +#include #ifdef CONFIG_SMP # include @@ -87,6 +88,41 @@ static void delay_tsc(unsigned long __loops) } /* + * On AMD platforms mwaitx has a configurable 32-bit timer, that counts + * with TSC frequency. And the input value is the loop of the counter, it + * will exit with the timer expired. + */ +static void delay_mwaitx(unsigned long __loops) +{ + u32 end, start, delay, addr, loops = __loops; + + rdtsc_barrier(); + rdtscl(start); + + for (;;) { + delay = min(MWAITX_MAX_LOOPS, loops); + + __monitorx(&addr, 0, 0); + /* + * AMD, like Intel, supports the EAX hint and EAX=0xf + * means, do not enter any deep C-state and we use it + * here in delay() to minimize wakeup latency. + */ + mwaitx(0xf, delay, true); + + rdtsc_barrier(); + rdtscl(end); + + if (loops <= end - start) + break; + + loops -= end - start; + + start = end; + } +} + +/* * Since we calibrate only once at boot, this * function should be set once at boot and not changed */ @@ -108,7 +144,10 @@ int read_current_timer(unsigned long *timer_val) void __delay(unsigned long loops) { - delay_fn(loops); + if (!static_cpu_has_safe(X86_FEATURE_MWAITT)) + delay_fn(loops); + else + delay_mwaitx(loops); } EXPORT_SYMBOL(__delay); -- 1.9.1